How do I add multiple AXI4 stream interfaces to a SoC block set design for building with SoC Builder

I am trying to use the SoC Blockset to build an RFSoC design that uses the RF Data Converter Block, the DDR memory controller(s), and the PS. The SoC builder workflow seems to nicely capture the whole model with both the PL and PS residing as referenced models under a top level hierarchy. The SoC blocksest provides the RF Data Converter, Memory access and register access for the processor however, I would like to stream data of the RFSoC using the high speed serial to implement an Aurora link. I am happy generating the Auruoa link in HDL, external to the model but I am unclear as to how to create the external connections in the model required.

The SoC builder tool seems to expect a SoC blockset block to be connected to any in or out port to the model thus I dont seem to be able to do use the automatic AXI Stream codeing implemented by creating a data and valid port for my interface.

Is there a method that allows SoC Builder to expose an AXI port that can be connected in something like Vivado, or better still allow whatever SoC builder creates to include a reference model with these interfaces?

cheers

Graham