how to write hdl testbench inside matlab using system clock delays for simulink hdl model verification?

Hi, can I write testbench for verilog/vhdl based simulink blackbox model, without exporting to HDL (xilinx-ISE/modelsim) simulator.

One big doubt is that, I am writing a mcode block sung simulink. When I write test vectors using matlab function, can I add a system delay, like advancing the clock for few time samples(with the current inputs as it is). While writing testbench in HDL files, this option is there, like in verilog we say " #10 ns; " and the system clock advances 10ns. How do we do this in matlab.

Answer 1

[Tim McBrayer]

I think what you are asking is, can you use a Simulink model to provide the stimulus to HDL code while the HDL simulates inside a 3rd party HDL simulator. if this is what you are asking, the answer is 'yes'. Simulink<-->HDL simulator cosimulation is provided by the HDL Verifier product.

HDL Verifier will take the Simulink data at the inputs of the cosimulation block and transmit it to the the HDL simulator (ModelSim or Cadence Incisive). It will then execute the HDL simulation for one clock cycle, and send the results generated on the HDL output ports back to Simulink. These results then propagate throughout the rest of the Simulink model like any other signals.

If you want to provide any specific time-based waveform to the HDL via the cosimulation block, you just need to generate that waveform in Simulink on the signals leading to the cosimulation block inputs.

[abc NP]

Hi Tim, Thanks for your answer. I got many confusions and most of them are cleared. Actually we have xilinx system generator tool license and I have mistaken that HDL coder and sysgen tool are same.

What I still don't understand is HDL model verification in system generator. Basically if I have a system design (containing a mix of sysgen simulink and blackbox models), and if I have to verify it, I am always exporting the generated netlist to the xilinx tool and writing a testbench there in HDL. Without that, if I have to verify it in simulink itself, by writing testbench in matlab, I am writing the testbench in matlab function block (given in user-defined function in simulink) and writing some test vectors in a function and I am defining the function without any inputs, so that the function looks like traditional HDL testbench. What I am searching here is, how to hold the testbench for n clock cycles. For example in verilog we say "#10 ns;" and the system waits for 2 clock cycles if we define clock period as 5 ns. I tried something like this (shown below) but I feel not satisfactory myself.

function [x,y,z....] = my_testbench

.....

.....

tic; while (toc <= 10e-9) end

....

....

end

Suppose we don't know the system clock (or how much period the system taken in critical path) and I want to input a vector [1 7 5....] to a particular port of xilinx model, how can I send each input in each sample time. The interesting problem I found here is, there is a provision in simulink "DSP system toolbox" and "signal from workspace" block. There I am able to input the vectors for the required n number of samples. But if I have to do it from matlab function, I am unable to search (in matlab website and google) any matlab function to grab the system sample time and hold it (or advance it) for n samples etc. Sorry, if the question is very lengthy, can you please help with this. If for this provision is not there and we have to use HDL verifier, its just a small functionality to advance the system samples for required clock cycles through matlab code. Can you please consider my suggestion of including this to future matlab versions, which looks very comfortable to the matlab users.