I am getting error and warning for the verilog code

Hi

for the given code why am i getting error and warning while simulating the said code.can you please help me by correecting the code or by pointing out my mistake.

module adder(A,B,sum);
parameter N=64;
input signed [N-1:0] A;
input signed [N-1:0] B;
output signed [N-1:0] sum;
assign sum = A+B;
endmodule

module multiplier(A,B,sum,clk);
parameter N=64;
input clk;
input signed [N-1:0] A;
input signed [N-1:0] B;
output reg signed [N-1:0] sum;
integer i;
always@(posedge clk)
begin
for (i=0;i<32;i=i+1)
begin
if (i!=32'd31)
 if (B[i]==1'b1)
   sum=sum+(A<<i);
else
 if (B[i]==1'b1)
   sum=sum-(A<<i);
end
end
endmodule



module Delay(clk,clr,in,out);
parameter N=64;
input clk,clr;
input signed [N-1:0] in;
output reg signed [N-1:0] out;
always@(posedge clk)
begin
 if(clr)
  out<=1'b0;
 else
  out<=in;
 end
endmodule


module stepsize_updatea(clk,clr,mu_EVSS,mu,mu_EXTRA,mu_min,mu_max);
parameter N=64;
input  [0:0] clr,clk;
input signed[N-1:0] mu,mu_min,mu_max,mu_EXTRA;
output reg signed [N-1:0] mu_EVSS;
always@(posedge clk)
begin
if (clr)begin
 mu_EVSS<=mu;
end
else begin
 mu_EVSS<= (mu > mu_min && mu < mu_max) ? (mu + mu_EXTRA) :
                 (mu <= mu_min) ? (mu >> 5) + mu_EXTRA :
                 (mu > mu_max) ? mu_max : mu_min;
end
end
endmodule

module coeff_update(clk,clr,k0,k1,k2,k3,k4,k5,k6,k7,h0,h1,h2,h3,h4,h5,h6,h7,p0,p1,p2,p3,p4,p5,p6,p7);
parameter N=64;
input clr,clk;
input signed [N-1:0] h0,h1,h2,h3,h4,h5,h6,h7,p0,p1,p2,p3,p4,p5,p6,p7;
output reg signed [N-1:0] k0,k1,k2,k3,k4,k5,k6,k7;

reg signed [N-1:0] mu_EVSS;

always@(posedge clk)
begin
if(clr) begin
 k0<=h0;
 k1<=h1;
 k2<=h2;
 k3<=h3;
 k4<=h4;
 k5<=h5;
 k6<=h6;
 k7<=h7;
end
else begin
 k0 <= p0;
 k1 <= p1;
 k2 <= p2;
 k3 <= p3;
 k4 <= p4;
 k5 <= p5;
 k6 <= p6;
 k7 <= p7;
 end
end
endmodule
 
module fir_filter_error(clk,clr,X,h0,h1,h2,h3,h4,h5,h6,h7,Y,d);
parameter N=64;
parameter U=10;
input signed [N-1:0] X,h0,h1,h2,h3,h4,h5,h6,h7,d;
output signed [N-1:0] Y;
input clk,clr;

wire signed [N-1:0] m1_out,d1_out,m2_out,d2_out,m3_out,d3_out,m4_out,d4_out,m5_out,d5_out,m6_out,d6_out,m7_out,d7_out;
wire signed [N-1:0] a1_out,a2_out,a3_out,a4_out,a5_out,a6_out;
wire signed[N-1:0] error;
wire signed [N-1:0] mu_EVSS;
coeff_update c1(clk,clr,k0,k1,k2,k3,k4,k5,k6,k7,h0,h1,h2,h3,h4,h5,h6,h7,p0,p1,p2,p3,p4,p5,p6,p7);
multiplier m1(X,h0,m1_out);
Delay d1(clk,clr,X,d1_out);
multiplier m2(d1_out,h1,m2_out);
Delay d2(clk,clr,d1_out,d2_out);
multiplier m3(d2_out,h2,m3_out);
Delay d3(clk,clr,d2_out,d3_out);
multiplier m4(d3_out,h3,m4_out);
Delay d4(clk,clr,d3_out,d4_out);
multiplier m5(d4_out,h4,m5_out);
Delay d5(clk,clr,d4_out,d5_out);
multiplier m6(d5_out,h5,m6_out);
Delay d6(clk,clr,d5_out,d6_out);
multiplier m7(d6_out,h6,m7_out);
Delay d7(clk,clr,d6_out,d7_out);
multiplier m8(d7_out,h7,m8_out);
adder a1(m1_out,m2_out,a1_out);
adder a2(a1_out,m3_out,a2_out);
adder a3(a2_out,m4_out,a3_out);
adder a4(a3_out,m5_out,a4_out);
adder a5(a4_out,m6_out,a5_out);
adder a6(a5_out,m7_out,a6_out);
adder a7(a6_out,m8_out,Y);

assign error=d-Y;
stepsize_updatea s1(clr,mu_EVSS,mu,mu_EXTRA,mu_min,mu_max);
multiplier m9(error,mu_EVSS,er_out);

assign p1=k1 + er_out*d1_out;
assign p2=k2 + er_out*d2_out;
assign p3=k3 + er_out*d3_out;
assign p4=k4 + er_out*d4_out;
assign p5=k5 + er_out*d5_out;
assign p6=k6 + er_out*d6_out;
assign p7=k7 + er_out*d7_out;

coeff_update c2(clk,clr,k0,k1,k2,k3,k4,k5,k6,k7,h0,h1,h2,h3,h4,h5,h6,h7,p0,p1,p2,p3,p4,p5,p6,p7);

endmodule

the testbench code

`timescale 1ns / 1ps

module adapt_test;
parameter N=64;
parameter mu=0.025;
parameter mu_min=0.0004;
parameter mu_max=0.025;


reg clk,clr;
reg signed [N-1:0] X,h0,h1,h2,h3,h4,h5,h6,h7,d;
wire signed [N-1:0] Y;
fir_filter_error main(clk,clr,X,h0,h1,h2,h3,h4,h5,h6,h7,Y,d);
initial begin
clk=0;
clr=1;
h0=64'b0;
h1=64'b01;
h2=64'b10;
h3=64'b11;	
h4=64'b11;
h5=64'b10;
h6=64'b01;
h7=64'b0;
X=0;
//d=1500;
d=1100;
//d=300;
//d=70;
#10 clr=0;

//#16 X= 32'd6;
#16 X=5;
//#16 X=11;

#400 $finish;
end


always #5 clk=~clk;

endmodule

Answer 1

[Sai]

Hi,

I understand that you are seeing verilog code problems, and from what I have observed, erroneous module instantiation is the root of the problem.

‘multiplier’ and ‘stepsize_updatea’ modules are frequently instantiated incorrectly in the ‘fir_filter_error’ module.

On instantiating, the module ‘multiplier’ declared only 3 of the expected 4 arguments.

The same thing occurred with another module called ‘stepsize updatea’, which was supposed to have 7 arguments but only received 6, as indicated.

Actual module: module multiplier(A,B,sum,clk); - 4 parameters;

Instantiated module: multiplier m1(X,h0,m1 out);, however it only has 3 parameters.

Actual module: module stepsize updatea(clk,clr,mu EVSS,mu,mu EXTRA,mu min,mu max); - 7 arguments;

Instantiated module: stepsize updatea s1(clr,mu EVSS,mu,mu EXTRA,mu min,mu max); - Obtained only 6

Regards,

G.saikumar,

MathWorks Technical Support

[PARVATHY NAIR]

thankyou @Sai

while simulating i am getting these warnings.why is it so?where am i wrong

[Sai]

As I can see, there are some port widths mismatch. Declared port in a module is expecting a data of 64 bits, where the same port in instantiated module is getting some other. Kindly look into that.