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In Simulink, why do two unrelated modules affect each other?

8 vues (au cours des 30 derniers jours)
ZF
ZF le 19 Juil 2024
Commenté : ZF le 22 Juil 2024
In Simulink, I created two computation modules A and B, as shown in Figure 1. Modules A and B are independent of each other and do not share any data. When A and B are not connected, the time history chart calculated by Module A is shown in Figure 1. However, when A is connected to B, Module A calculates a different time history chart, as shown in Figure 2. Note that Module B does not form a closed-loop with Module A. Why does this situation occur? I would appreciate it if anyone could tell me the reason, thank you very much.
Additionally, I found that as long as module A is connected with the transfer function module (without forming a closed-loop circuit), the time course graph on the oscilloscope will change.

Réponses (1)

Paul
Paul le 19 Juil 2024
Even if A and B are not connected, changes in B can causes changes in output of A because those changes in B can affect the step size in the solver. Whether or not that is the case depends on your solver settings and whether or not you have the optimization turned on to not execute blocks that don't need to be executed, which appears to be the case in the first instance as (it appears) there are no signals being logged from B.
In the second case, connecting B to A could affect the step size of the solver as compared to the unconnected case, again depending on your solver settings.
The default solver settings use a variable step solver, so if you haven't changed from the default that's probably what's happening. A quick check would be to run both configurations and compare the tout (default name) output variable from the simulation so you can compare the simulation step times from both cases.
  5 commentaires
Paul
Paul le 22 Juil 2024
You're very welcome.
Would you mind providing a bit more detail on what the warning was and how it was addressed to solve the problem? Might be useful for others that might run into the same situation.
ZF
ZF le 22 Juil 2024
Of course. An 'algebraic loop(s)' was generated in the original architecture, as shown by the diagnosis in Figure 1. I added 'memory blocks', which seems to have eliminated the 'algebraic loop(s)'. I'm not exactly sure why. But it appears that the problem has been resolved.

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