Integrating HDL Coder, System Generator and VHDL/Verilog projects

Hello,

we plan to integrate several HDL coder, system generator and VHDL/Verilog units into one bigger project. I already have experience with implementing such units singly onto one FPGA device but I don't have an idea how to combine them. I am using the Xilinx tool suite (XPS, SDK, ISE).

Has anyone experience with that or knows were to find documentation and/or tutorials for such integration?

A detailed question I have is how I can access resources created in system generator in HDL coder? Is it possible to access registers/specific signals with HDL coder or is the abtraction level too high for that?

Thanks in advance and best regards, Tom

[vidya shree]

Hi,iam doing project on face recognition using lbp on fpga based soc So im using matlab code and then convert to hdl code and then use fgpa So any1 plzzz help me out to do this ,this code conversion and fpga implementation

Answer 1

[Tim McBrayer]

If you really need to combine disparate sets of code into one project, the most obvious approach is to design your overall hierarchy and have each set of generated code connected to the appropriate others via a handwritten top level wrapper.

Beyond this, HDL Coder has the capability to combine code within its framework. You can include arbitrary code at an arbitrary location using the black box functionality. This code can be hand written or, it can be generated by HDL Coder, or by any other tool.

If the code was generated from a separate Simulink model, you can consider using a model reference block to reference the other model in Simulink and to generate HDL code for the combined design at the same time. HDL Coder also allows the embedding of System Generator subsystems within it.