Where to find the default HDL project for ZedBoard or ZCU102 FMCOMMS2/3/4 Xilinx Zynq-Based Radio Linux image?

Hi,

The Communications Toolbox Support Package for Xilinx Zynq-Based Radio uses a default operating system image, which is written to the SD card during the Hardware Setup process.

My question is: where can I find the HDL Coder (or Vivado) project that generates the same FPGA bitstream (system.bit) used in this default Linux image?

More specifically, I am looking for a MATLAB/HDL-based reference project that produces exactly the same bitstream as the one included in the prebuilt Linux image provided by the support package, and then I can program my target with that.

Is this reference HDL project available to users?

If not, is there documentation describing how the default bitstream was generated and how to reproduce it?

Thank you.

Answer 1

[Lakshmi Bugide]

Hi,

If you want to create your own bitstream, you would use HDL Coder with the HDL Workflow Advisor.

1. Create your own Simulink Passthrough model with a Simulink subsystem
2. Use HDL Workflow Advisor to generate an HDL IP core
3. Select the appropriate SDR reference design target and Reference Design.
4. HDL Coder will integrate your IP core with the reference design and generate a new bitstream through Vivado.

The documentation Hardware-Software Co-Design Workflow - MATLAB & Simulink mentions this workflow in the Hardware/Software Co-design documentation.

But, the default reference HDL project is not available for user and also there is no documentation describing how the default bitstream was generated and how to reproduce it.

Thanks,

Lakshmi

[User_Hos]

Thanks, I'll follow the link