How to generate VHDL code in Xilinx for discrete PID controller for the controller equation is as u(k)=u(k-1)+(28.2671)e(k)+(-55.5204)e(k-1)+(27.2625)e(k-2) ????

3 vues (au cours des 30 derniers jours)

Harshit Derasari le 25 Fév 2018

the algorithm is Distributed Arithmetic(DA) algorithm based on LUTs(Look up tables)

En savoir plus sur Xilinx FPGA and SoC Devices dans Help Center et File Exchange

Find the treasures in MATLAB Central and discover how the community can help you!

Translated by

How to generate VHDL code in Xilinx for discrete PID controller for the controller equation is as u(k)=u(k-1​)+(28.2671​)e(k)+(-55​.5204)e(k-​1)+(27.262​5)e(k-2) ????