question on Performing Large Matrix Operation on FPGA using External Memory

I am currently using Matlab 2018a to run the demo "Performing Large Matrix Operation on FPGA using External Memory". Targeting to Arria 10 SoC Development Kit. It looks 512 bits are read out from DDR4(@1066.667MHz actually) and then transmitted via MATLAB_as_AXI_Master(@100 MHz) by 32bit times 8 cycles. So my question is how can I increase this bit width(32bit here) as high as possible?

[Tao Jia]

There is a data_width parameter on the MATLAB_as_AXI_Master IP. If you open Qsys, you can set it to 64. Currently we only support 32 and 64bit data width.

The performance bottleneck is typically the JTAG transfer speed to the host computer. If you increase the bit width on the AXI interface, it is unlikely to increase the performance much.