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ZedBoard FIL example does not run with R2018a

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Mike Bardill
Mike Bardill on 18 Apr 2019
I have been running the example "Verify HDL Implementation of PID Controller Using FPGA-in-the-loop" on a ZedBoard using R2018a. The help for the example instructs to copy the fil_pid model and VHDL source files from the installation into a local folder. Having run through the FPGA-in-the-Loop Wizard the example ran through to completion and simulated correctly on the target FPGA with JTAG communication.
I then regenerated the Controller VHDL files using Generate HDL for Subsystem. I did not change any model configuration settings. The build completed but when I tried to run it failed with an error in a Mex file in the Diagnostics window. The error did not give any other useful information.
I noticed that the VHDL copied from the installation and that generated with R2018a were different. Specifically the generated VHDL has an additional ce_out output port.
The only way I could find to remove the ce_out port is to set the option "Minimize clock enables"; however, this removes both the clk_enable and ce_out ports from the Controller VHDL. This then builds and runs successfully on the target.
Do the clk_enable and ce_out ports have some critical interraction with the FIL running and if so what is the correct configuration setting to use to ensure that the generated VHDL is compatible with FIL?
Built with R2018a
ENTITY Controller IS
PORT( clk : IN std_logic;
reset : IN std_logic;
error_d : IN std_logic_vector(31 DOWNTO 0); -- sfix32_En16
control_signal : OUT std_logic_vector(31 DOWNTO 0) -- sfix32_En28
);
END Controller;
as copied from installation:
ENTITY Controller IS
PORT( clk : IN std_logic;
reset : IN std_logic;
clk_enable : IN std_logic;
error_d : IN std_logic_vector(31 DOWNTO 0); -- sfix32_En16
control_signal : OUT std_logic_vector(31 DOWNTO 0) -- sfix32_En28
);
END Controller;

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