I have written a verilog program in which some of lines of code runs based on positive edge of clock pulse (Ex: always @ (posedge clk) ). Therefore, the code requires a clock (clk) as one of the inputs. Assigning clock pulse as an input in the target device CMOD S6 (spartan 6) is possible and hence programming/flashing CMOD S6 become success. Also verified that the obtained output results are satisfactory.
Instead of flashing an external real world FPGA, I wish to flash the above code into the internal FPGA of Opal-RT target device OP4510 using system generator 14.7. However, I got stuck in accessing FPGA clock which is required, as I said before, as an input for the code. I have tried to use pulse generator as a clock input but can not set its frequecy as 8MHz (desired clock frequecy) due to simulation step time limitation.
I would be thankful for the relevant responses.