FIL Wizard giving me a strange error
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Hey all,
I'm trying to make a FIL model using the FPGA in the loop wizard. I've done this successfully before, I am simply doing it again with a different vhdl file. I go through all of the options, Hardware Options, Source Files, I/O Ports, and then I get to Build Options. When I select "Build" it halts and gives me an error at the bottom that says: "Error: Parameter 'taret_language' does not exist in the param repository." Taret is misspelled in the error. The vhdl file I am using has been simulated and runs fine in the simulator, I'm not sure what this error is - I have never seen it before. Any advice would be welcome
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