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Question
Unable to See the Constant Sine Wave Data in NI FPGA After Some Time Duration.
Hello, I have created a sine wave FPGA bitfile using a Simulink block. In this model, I replaced the Clock block with a Counter...
11 mois il y a | 1 réponse | 0
1
réponseQuestion
Changing Limiting the number of logged data points to the last 50000
hello currently i am exporting Simulink model to App but when its converting i am getting this information like Limiting t...
environ un an il y a | 1 réponse | 0
1
réponseQuestion
Could not apply model's TargetPlatform settings in Task 1.1 of the HDL Workflow Advisor
Hello, I am currently working on converting a Simulink model to an NI FPGA Bitfile. Recently, I updated LabVIEW from the 2023 v...
plus d'un an il y a | 1 réponse | 1
1
réponseQuestion
the compilation failed due to timing violation
Hello, I am working on generating an NI FPGA Bitfile from Simulink. During the generation process, I encountered an error. I ha...
plus d'un an il y a | 1 réponse | 0
1
réponseQuestion
HDL and NI FPGA code generation error.
Hello, I am attempting to generate spike voltage using a MATLAB Function block in Simulink. While the function block successful...
plus d'un an il y a | 1 réponse | 0
1
réponseQuestion
Getting error while using .m files in MATLAB function block in simulink.
Hello, I am currently working on creating a custom RMS block within MATLAB's Simulink environment. My goal is to replicate the...
plus d'un an il y a | 1 réponse | 0
1
réponseQuestion
how to reduce Estimated Slice LUTs Utilization in FPGA code generation process.
Hello, I am working on generating a bitfile from a Simulink model. While converting, the Simulink model is using more slice LUTs...
plus d'un an il y a | 1 réponse | 0
1
réponseQuestion
Assertion failed error while convereting simulink model to HDL code
hello sir , i am using MATLAB 2022b version in that while converting simulink model to NI FPGA bit files , in HDL Work flow adv...
plus d'un an il y a | 1 réponse | 0
