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Example HDL QAM : changing QAM 64 to QAM 256
It looks like you are stuck modifying the existing to QAM 256. Please reach out to tech support for additional guidance. They ca...

plus de 2 ans il y a | 0

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Can I use HDL Coder without a Vivado license in my machine?
HDL Coder generates synthesizable VHDL and Verilog code. You can use the target settings to customize the code for a specific ha...

presque 3 ans il y a | 0

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What are MIL, SIL, PIL, and HIL, and how do they integrate with the Model-Based Design approach?
“M”, “S”, “P” and “H” are all referring to the Controller. PIL uses the Controller Processor only (no I/O connectivity), HIL ...

presque 3 ans il y a | 2

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Error: variable-size matrix type is not supported for HDL code
Variable dimensions are not synthesizable to hardware and hence not supported for HDL Code generation. >> mlhdlc_demo_setup...

presque 3 ans il y a | 0

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import hdl coder fails, why?
This is a limitaiton of importhdl feature. In general only subset of verilog is convertible to Simulink using this feature.

presque 3 ans il y a | 0

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When using Simulink External Mode with an AXI4-Stream IIO Read block, if the timeout value is greater than zero, it cause the simulation time to be slower than actual time
The timeout behavior is expected, the timeout leads to overrun in the software task and so the time step will get out of sync wi...

presque 3 ans il y a | 0

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Issue in HDL Coder
t = 1:10; x = [4 8 6 -1 -2 -3 -1 3 4 5]; yc = movmean(x,5); plot(t,x,t,yc); The movemean fun...

presque 3 ans il y a | 0

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Issue in HDL Coder
Can you share the design, testbench and project files? Feel free to reach out to MathWorks tech support or DM me with the repro...

presque 3 ans il y a | 0

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Errors : algebraic loop in use HDL simulink coder
https://www.mathworks.com/matlabcentral/answers/95310-what-are-algebraic-loops-in-simulink-and-how-do-i-solve-them Models with ...

presque 3 ans il y a | 0

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error HDL compilation failed
Can you check if all the design files are added to the filWizard? There seems to be a pilot error and some package files are mis...

presque 3 ans il y a | 0

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select MIcrochip Libero as target and get error saying "Index exceeds the number of array elements. Index must not exceed 0."
https://www.mathworks.com/support/bugreports/2772641 This is a known issue addressed in the R2022b Update3 and the recent R20...

presque 3 ans il y a | 1

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Assertion failed: b:\matlab\src\cgir_hdl\target_analysis\characterizationkeygenerator.cpp:45:val
https://www.mathworks.com/help/hdlcoder/ug/find-estimated-critical-paths-without-synthesis-tools.html Critical Path Estimation ...

presque 3 ans il y a | 0

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MATLAB compatibility with VIVADO 2018.2 and VIVADO 2019.2
https://www.mathworks.com/matlabcentral/answers/518421-which-versions-of-xilinx-vivado-are-supported-with-which-release-of-hdl-c...

presque 3 ans il y a | 0

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Error Goto/From connections subsystem boundaries
https://www.mathworks.com/help/hdlcoder/ug/deploy-buck-converter-to-speedgoat-io-modules-workflow-script.html Deploy Simscape...

presque 3 ans il y a | 0

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Unsupported dimensions of matrix type at output port 0
Matrices are supported at the DUT boundary in HDL Coder https://www.mathworks.com/help/hdlcoder/io-optimization.html?s_tid=CRUX...

presque 3 ans il y a | 0

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Introduce Zybo board in Simulink HDL coder workflow advisor
https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-and-reference-design-for-zynq-workflow.html This ex...

presque 3 ans il y a | 0

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I am having a problem in converting matlab to vhdl code
Consider reviewing the example below for best practices for MATLAB to HDL code generation. >> mlhdlc_demo_setup('mlhdlc_fft_cha...

presque 3 ans il y a | 0

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xilinx blockset is not shown in simulink library
https://www.xilinx.com/products/design-tools/vitis/vitis-model-composer.html Vitis Model Composer by: Xilinx, Inc Vitis™ Mode...

presque 3 ans il y a | 0

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Simulink models to Verilog HDL coder
Matrix IO is now supported with HDL Coder https://www.mathworks.com/help/hdlcoder/io-optimization.html?s_tid=CRUX_topnav htt...

presque 3 ans il y a | 0

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Xilinx Zynq ZCU104 evaluation board support
Customizing HDL Coder workflow for ZCU104 board: https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-an...

presque 3 ans il y a | 0

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SoC Builder fails to deploy on Xilinx ZCU104 FPGA Board
HDL Coder workflow to add a custom ZCU104 board https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-and...

presque 3 ans il y a | 0

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Adding Xilinx ZCU104 board to SoC Blockset
Customizing the HDL Coder workflow for ZCU104 board: https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-boar...

presque 3 ans il y a | 0

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Deep Learning HDL Toolbox - HDL generation
https://www.mathworks.com/help/deep-learning-hdl/ug/define-custom-board-and-reference-design-for-dl-ip-core-workflow.html Deep ...

presque 3 ans il y a | 0

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E310/HDL Coder - How can I design a model where the ARM application individually requests frames of samples from the E310 Receiver/FPGA?
HW/SW Codesign workflow of SDR algorithms for USRP™ embedded series radio hardware This guide helps you to deploy partitioned...

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How to convert the Simulink project to VHDL code?
Implement Digital Downconverter for FPGA This example shows how to design a digital downconverter (DDC) for radio communication...

presque 3 ans il y a | 0

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MATLAB stuck when HDL coder converted the model to Verilog
Can you share your model or reach out to tech support for further guidance on the topic? In general this model seems to be usin...

presque 3 ans il y a | 0

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Compiling fixedpt converted code into VHDL
https://www.mathworks.com/help/hdlcoder/gs/generate-hdl-code-from-matlab-code-using-the-command-line-interface.html Generate HD...

presque 3 ans il y a | 0

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HDL coder error,Call to function 'fmod' is not supported for HDL code generation,
This message scenerio happens when HDL Coder finds an unsupported function error. Can you share a sample MATLAB code and Testb...

presque 3 ans il y a | 0

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In Simulink HDLcoder, which converts a model into a hardware description language, it's stuck in this interface
I wonder if the model has unsupported constructs for HDL Code Generation. However you should recieve an early warning about the ...

presque 3 ans il y a | 0

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HDL Coder Example for ZedBoard
Can you review this shipping example? It should be customizable for your usecase. Generate IP Core from MATLAB for Blinking LED...

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