Convolutional Encoder
Encode binary data using convolutional encoding scheme
Libraries:
Communications Toolbox /
Error Detection and Correction /
Convolutional
Communications Toolbox HDL Support /
Error Detection and Correction /
Convolutional
Description
The Convolutional Encoder block encodes the input binary message by using the convolutional encoding scheme specified by a trellis structure. For more information, see Convolutional Coding.
This block can accept inputs that vary in length during simulation. For more information about variablesize signals, see the VariableSize Signal Basics (Simulink) topic.
These icons show the optional block ports enabled.
Examples
Compute SER of Convolutionally Encoded Signal
Apply convolutional encoding and BPSK modulation to a binary signal, pass the modulated signal through an AWGN channel. Compute the symbol error rate (SER) of the signal after applying BPSK demodulation and Viterbi decoding.
Explore model
The doc_conv model generates a binary signal by using a Bernoulli Binary Generator block. The Convolutional Encoder block encodes the signal. The BPSK Modulator Baseband block modulates the signal. The AWGN Channel block adds noise to the signal. To demodulate the BPSK modulated signal with zero phase shift, simply extract the value of the real component of the complex symbol demodulation by using the Complex to RealImag (Simulink) block. The Viterbi Decoder block decodes the signal. The Error Rate Calculation block computes the SER.
Run simulation
ans = 'Filtering the signal through an AWGN channel with the EsN0 set to 1 dB, the computed SER is 0.005608.' ans = 'For 53499 transmitted symbols, there were 300 symbols errors.'
Punctured Convolutional Coding in Simulink
This example simulates a punctured coding system that uses rate 1/2 convolutional encoding and Viterbi decoding. The complexity of a Viterbi decoder increases rapidly with the code rate. The puncturing technique enables encoding and decoding of higher rate codes by using standard lower rate coders.
The cm_punct_conv_code
model transmits a convolutionally encoded BPSK signal through an AWGN channel, demodulates the received signal, and then performs Viterbi decoding to recover the uncoded signal. To compute the error rate, the model compares the original % signal and the decoded signal.
The model uses the PreloadFcn
callback function to set these workspace variables for initialization of block parameters:
puncvec = [1;1;0;1;1;0]; EsN0dB = 2; traceback = 96; % Viterbi traceback depth
For more information, see Model Callbacks (Simulink).
The blocks in this model perform these operations:
Bernoulli Binary Generator — Sets Sample per frames to
3
. The block creates a sequence of random bits outputting three samples per frame at each sample time.Convolutional Encoder — Uses the default setting for Trellis structure, selects Puncture code, and sets Puncture vector to the workspace variable
puncvec
. The block encodes frames of data by puncturing a rate 1/2, constraint length 7 convolutional code to a rate 3/4 code. The puncture vector specified bypuncvec
is the optimal puncture vector for the rate 1/2, constraint length 7 convolutional code. A1
in the puncture vector indicates that the bit in the corresponding position of the coded vector is sent to the output vector, while a0
indicates that the bit is removed. For the configured encoder, coded bits in positions 1, 2, 4, and 5 are transmitted, while bits in positions 3 and 6 are removed. The rate 3/4 code means that for every 3 bits of input, the punctured code generates 4 bits of output.BPSK Modulator Baseband — Modulates the encoded message using default parameter values.
AWGN Channel — Sets Mode to
Signal to noise ratio (Es/No)
and setsEs/No (dB)
to the workspace variableEsN0dB
. Since the modulator block generates unit power signals, Input signal power, referenced to 1 ohm (watts) keeps its default value of1
.Viterbi Decoder — Uses settings for Trellis structure, Punctured code, and Puncture vector that align with the Convolutional Encoder block. The block sets Decision type to
Unquantized
and Traceback depth to thetraceback
workspace variable. To decode the specified convolutional code without puncturing the code, a traceback depth of 40 is sufficient. However, to give the decoder enough data to resolve the ambiguities introduced by the punctures, the block uses a traceback depth of 96 to decode the punctured code. Similar to the convolutional encoder, the puncture vector for the decoder indicates the locations of the punctures. For the decoder, the locations are bits to ignore in the decoding process because the punctured bits are not transmitted and there is no information to indicate their values. Each 1 in the puncture vector indicates a transmitted bit, and each 0 indicates a punctured bit to ignore in the input to the decoder.Complex to RealImag (Simulink) — Demodulates the BPSK signal by extracting the real part of the complex samples.
Error Rate Calculation — Uses the Receive delay value to account for total number of samples of system delay and compares the decoded bits to the original source bits. The block outputs a threeelement vector containing the calculated BER, the number of errors observed, and the number of bits processed. The Receive delay is set to the
traceback
workspace variable because the Viterbi traceback depth causes the only delay in the system. Typically, BER simulations run until a minimum number of errors have occurred, or until the simulation processes a maximum number of bits. The Error Rate Calculation block selects the Stop simulation parameter and sets the target number of errors to100
and the maximum number of symbols to1e6
to control the duration of the simulation.
Evaluate Bit Error Rate
Generate a bit error rate curve by running this code to simulate the model over a range of EbN0 settings.
Compare the simulation results with an approximation of the bit error probability bound for a punctured code as per [ 1 ]. The bit error rate performance of a rate punctured code is bounded above by the expression:
In this expression, erfc
denotes the complementary error function, is the code rate, and both and are dependent on the particular code. For the rate 3/4 code of this example, = 5, = 42, = 201, = 1492, and so on. For more information, see reference [ 1 ].
Compute an approximation of the theoretical bound using the first seven terms of the summation for Eb/N0 values in 2:0.02:5
. The values used for nerr
come from reference [ 2 ], Table II.
Plot the simulation results, a fitted curve, and theoretical bounds.
In some cases, at the lower bit error rates, you might notice simulation results that appear to indicate error rates slightly above the bound. This result can come from the finite traceback depth in the decoder or, if you observe fewer than 500 bit errors, from simulation variance.
For an example that shows convolutional coding without puncturing, see the SoftDecision Decoding section in Error Detection and Correction.
References
Yasuda, Y., K. Kashiki, and Y. Hirata, "High Rate Punctured Convolutional Codes for Soft Decision Viterbi Decoding," IEEE Transactions on Communications, Vol. COM32, March, 1984, pp. 315–319.
Begin, G., Haccoun, D., and Paquin, C., "Further results on HighRate Punctured Convolutional Codes for Viterbi and Sequential Decoding," IEEE Transactions on Communications, Vol. 38, No. 11, November, 1990, p. 1923.
Compare FixedPoint Viterbi Decoding to Theoretical Calculations
Use the Viterbi Decoder block for fixedpoint hard and softdecision convolutional decoding. Compare results to theoretical upper bounds as computed with the Bit Error Rate Analysis app.
Simulation Configuration
The cm_viterbi_harddec_fixpt
and cm_viterbi_softdec_fixpt
models highlight the fixedpoint modeling attributes of the Viterbi decoder, using similar layouts. The default configuration of the models use the PreLoadFcn
Callback to specify an setting of 4 dB for the AWGN Channel block. The convolutional encoder is configured as a rate 1/2 encoder. Specifically, for every 2 bits the encoder adds another 2 redundant bits. To accommodate the code rate, the Eb/No (dB) parameter of the AWGN block is halved by subtracting 10*log10(2)
from the assigned setting. To limit the run duration to 100 errors or 1e6 bits for the Error Rate Calculation block.
FixedPoint Modeling
Fixedpoint modeling enables bittrue simulations which take into account hardware implementation considerations and the dynamic range of the data and parameters. For example, if the target hardware is a DSP microprocessor, some of the possible word lengths are 8, 16, or 32 bits, whereas if the target hardware is an ASIC or FPGA, there may be more flexibility in the word length selection.
To enable fixedpoint Viterbi decoding,
For hard decisions, the block input must be of type ufix1 (unsigned integer of word length 1). Based on this input (either a 0 or a 1), the internal branch metrics are calculated using an unsigned integer of word length = (number of output bits), as specified by the trellis structure (which equals 2 for the harddecision example).
For soft decisions, the block input must be of type ufixN (unsigned integer of word length N), where N is the number of softdecision bits, to enable fixedpoint decoding. The block inputs must be integers in the range 0 to . The internal branch metrics are calculated using an unsigned integer of word length = (N + number of output bits  1), as specified by the trellis structure (which equals 4 for the softdecision example).
The State metric word length is specified by the user and usually must be greater than the branch metric word length already calculated. You can tune this to be the most suitable value (based on hardware and data considerations) by reviewing the logged data for the system.
Enable the logging by selecting Apps > FixedPoint Tool. In the FixedPoint Setting menu, set the Fixedpoint instruments mode to Minimums, maximums and overflows
, and rerun the simulation. If you see overflows, it implies the data did not fit in the selected container. You could either try scaling the data prior to processing it or, if your hardware allows, increase the size of the word length. Based on the minimum and maximum values of the data, you are also able to determine whether the selected container is of the appropriate size.
Try running simulations with different values of State metric word length to get an idea of its effect on the algorithm. You should be able to narrow down the parameter to a suitable value that has no adverse effect on the BER results.
The hard decision configuration for the cm_viterbi_harddec_fixpt
model:
The BPSK Demodulator Baseband produces hard decisions, which are passed onto the decoder.
The Data Type Conversion (Simulink) block sets the
Mode
parameter toFixed point
and casts the output data type tofixdt(0,1,0)
. The signal input to the Viterbi Decoder block isufix1
.
The Viterbi Decoder block has the
Decision type
parameter set toHard decision
, and on the Data Types tab, theState metric word length
is set to4
and theOutput data type
is set toboolean
. The bit error rate is displayed and captured to theBER
workspace variable.
The soft decision configuration for the cm_viterbi_softdec_fixpt
model:
The BPSK Demodulator Baseband produces soft decisions using the loglikelihood ratio. These soft outputs are 3bit quantized and passed onto the decoder.
A Quantizer subsystem (containing Gain (Simulink), Scalar Quantizer Encoder, and Data Type Conversion (Simulink) blocks) quantizes the signal and casts the output data type to
fixdt(0,3,0)
. The signal input to the Viterbi Decoder block isufix3
.
The Viterbi Decoder block has the
Decision type
parameter set toSoft decision
andNumber of soft decision bits
set to 3, and on the Data Types tab, theState metric word length
is set to6
and theOutput data type
is set toboolean
. The bit error rate is displayed and captured to theBER
workspace variable.
Comparisons Between Hard and SoftDecision Decoding
The two models are configured to run from within the Bit Error Rate Analysis app to generate simulation curves to compare the BER performance for harddecision versus softdecision decoding.
You can produce the results in this plot by following the steps outlined below.
These steps generate simulation results for theoretical and fixedpoint hard and soft decision Viterbi decoding:
Open the Bit Error Rate Analysis app by selecting it in the Apps tab or by entering
bertool
at the MATLAB command prompt.On the Theoretical pane, with Eb/N0 range set to 2:5, Channel type set to
AWGN
, Modulation type set toPSK
, Channel coding set toConvolutional
, run with Decision method set toHard
and thenSoft
. Rename the BER Data Set to identify the hard and soft data sets of theoretical results.On the Monte Carlo pane, set Eb/N0 range to 2:1:5, for Simulation environment select
Simulink
, BER variable name set toBER
, for Simulation limits set Number of errors to 100 and Number of bits to 1e6. Run with Model name set tocm_viterbi_harddec_fixpt
and thencm_viterbi_softdec_fixpt
. Rename the BER Data Set to identify the hard and soft data sets of Simulink results.
After the four runs the app will resemble this image.
Comparisons with DoublePrecision Data
For further explorations, you can run the same model with double precision data by selecting Apps > FixedPoint Tool
. In the FixedPoint Tool
app, select the Data type override
to be Double
. This selection overrides all data type settings in all the blocks to use double precision. For the Viterbi Decoder block, as Output type
was set to boolean
, this parameter should also be set to double
.
Upon simulating the model, note that the doubleprecision and fixedpoint BER results are the same. They are the same because the fixedpoint parameters for the model have been selected to avoid any loss of precision and optimize memory efficiency.
Extended Examples
TailBiting Convolutional Coding
Use the Convolutional Encoder and Viterbi Decoder blocks to simulate a tailbiting convolutional code.
Ports
Input
In — Input message
binary column vector
Input message, specified as a binary column vector. This port is unnamed until a second input port is enabled. If the encoder takes K input bit streams (that is, it can receive 2^{K} possible input symbols), the block input vector length is L×K for some positive integer L.
Example: [1 1 0 1 0 0 1 1]
specifies the message as
a binary row vector with eight elements.
Data Types: double
 single
 Boolean
 int8
 int16
 int32
 uint8
 uint16
 uint32
 ufix1
ISt — Initial state of encoder registers
nonnegative integer
Initial state of encoder registers for every frame input to the block, specified as a nonnegative integer.
Dependencies
To enable this port set the Operation
mode parameter to Truncated (reset every
frame)
and select Specify initial state
via input port.
Data Types: double
 uint32
Rst — Reset state of encoder registers
scalar
Reset state of encoder registers, specified as scalar value. Any nonzero value forces a reset of the encoder registers.
Dependencies
To enable this port set the Operation
mode parameter to Reset on nonzero input
via port
.
Data Types: double
 Boolean
Output
Out — Convolutionally encoded codeword
binary column vector
Convolutionally encoded codeword, returned as a binary column vector.
This port is unnamed on the block icon. If the encoder produces N output bit streams (that is, it can
produce 2^{N}
possible output symbols), the block output vector length is L×N for
some positive integer L. This output
inherits its data type from the In
input.
Data Types: double
 single
 Boolean
 int8
 int16
 int32
 uint8
 uint16
 uint32
 ufix1
FSt — Final state of encoder registers
nonnegative integer
Final state of encoder registers for every frame output from the block, returned as a nonnegative integer.
Dependencies
This parameter appears only when you set the Operation mode parameter to
Continuous
, Truncated
(reset every frame)
, or Reset on
nonzero input via port
and you select the
Output final state
parameter.
Data Types: double
Parameters
To edit block parameters interactively, use the Property Inspector. From the Simulink^{®} Toolstrip, on the Simulation tab, in the Prepare gallery, select Property Inspector.
Trellis structure — Trellis description of convolutional code
poly2trellis(7, [171 133])
(default)
Trellis description of the convolutional code, specified as a structure that contains the trellis description for a rate K ∕ N code. K is the number of input bit streams, and N is the number of output bit streams.
You can either use the poly2trellis
function to
create the trellis structure or create it manually. For more about this
structure, see Trellis Description of a Convolutional Code and the
istrellis
function.
The trellis structure contains these fields.
numInputSymbols — Number of symbols input to encoder
2^{K}
Number of symbols input to the encoder, specified as an integer equal to 2^{K}, where K is the number of input bit streams.
numOutputSymbols — Number of symbols output from encoder
2^{N}
Number of symbols output from the encoder, specified as an integer equal to 2^{N}, where N is the number of output bit streams.
numStates — Number of states in encoder
power of 2
Number of states in the encoder, specified as a power of 2.
nextStates — Next states
matrix of integers
Next states for all combinations of current states and current inputs, specified
as a matrix of integers. The matrix size must be numStates
by
2^{K}.
outputs — Outputs
matrix of octal numbers
Outputs for all combinations of current states and current inputs, specified as a matrix of
octal numbers. The matrix size must be numStates
by
2^{K}.
Operation mode — Termination method of encoded frame
Continuous
(default)  Truncated (reset every frame)
 Terminate trellis by appending bits
 Reset on nonzero input via port
Termination method of the encoded frame, specified as one of these mode values.
Continuous
— The block retains the encoder states at the end of each input for use with the next frame.Truncated (reset every frame)
— The block treats each input independently. At the start of each input frame, the encoder states are reset to allzeros state, or if you select Specify initial state via input port, to the state specified by theISt
port.Terminate trellis by appending bits
— The block treats each input independently. For each input frame, extra bits are used to set the encoder states to allzeros state at the end of the frame. The output length is given by y = N × (x + s) / K, where x is the number of input bits, and s = constraint length – 1 (or, in the case of multiple constraint lengths, s =sum(constraint length(i) – 1)).Note
This block works for cases K ≥ 1, where it has the same values for constraint lengths in each input stream. For example, constraint lengths of [2 2] or [7 7] will work, but [5 4] will not.
Reset on nonzero input via port
— The block has an additional input port, labeledRst
. When theRst
input is nonzero, the encoder resets to the allzeros state.
Note
When this block outputs sequences that vary in length during
simulation and you set the Operation mode to
Truncated (reset every frame)
or
Terminate trellis by appending bits
, the
block's state resets at every input time step.
Delay reset action to next time step — Option to delay reset action until next time step
off
(default)  on
Select this parameter to reset the block after computing the encoded data. The delay in the reset action allows the block to support HDL code generation. Generating HDL code, requires HDL Coder™ software.
Dependencies
This parameter appears only when you set the Operation mode parameter to Reset on
nonzero input via port
.
Specify initial state via input port — Option to specify initial state via input port
off
(default)  on
Select this parameter to add the ISt
input port to
the block.
Dependencies
This parameter appears only when you set the Operation mode parameter to Truncated
(reset every frame)
.
Output final state — Option to output final register state
off
(default)  on
Select this parameter to add the FSt
output port to
the block.
Dependencies
This parameter appears only when you set the Operation mode parameter to
Continuous
, Truncated (reset
every frame)
, or Reset on nonzero input
via port
.
Puncture code — Option to enable the code puncturing
off
(default)  on
Select this parameter to view and enable the Puncture vector parameter.
Puncture vector — Puncture pattern
[1; 1; 0; 1; 0; 1]
(default)  column vector
Puncture pattern, specified as vector. The puncture vector is a pattern of
1
s and 0
s where the
0
s indicate the bits punctured in the output encoded
data. The length of the vector must be an integer divisor of
length(
, the input
message vector length.In
)
For some commonly used puncture patterns for specific rates and polynomials, see the Yasuda [3], Haccoun [4], and Begin [5] references.
Dependencies
This parameter appears only when you select the Puncture code parameter.
Block Characteristics
Data Types 

Multidimensional Signals 

VariableSize Signals 

^{a} ufix(1) only. 
More About
Convolutional Coding
Convolutional coding is an errorcontrol coding that has memory. Specifically, the computations and coded output depend on the current set of input symbols and on a number of previous input symbols that varies depending on the trellis configuration. A convolutional encoder outputs N bits for every K input bits. The input can have varying multiples of K bits over a simulation.
Using a MATLAB^{®} trellis structure that defines a set of generator polynomials, you can model nonsystematic, systematic feedforward, or systematic feedback convolutional codes. For more information and examples that demonstrate various convolutional code architectures, see the Convolutional Codes topic.
To decode the convolutionally coded output, you can use:
The Viterbi Decoder block — Uses the Viterbi algorithm with harddecision and softdecision decoding
The APP Decoder block — Uses an a posteriori probability decoder for the soft output decoding of convolutional codes
To define the convolutional encoder, use the Trellis
structure parameter. You can specify the trellis structure with a
call to the poly2trellis
function. For more
information, see Trellis Description of a Convolutional Code.
For example, to use an encoder with a constraint length of 7, code generator polynomials of 171 and 133 (in octal numbers), and a feedback connection of 171 (in octal), set the Trellis structure parameter to
poly2trellis(7,[171 133],171)
poly2trellis
, and then specify the
variable name in the Trellis structure parameter.Simulink spends less time updating the diagram at the beginning of each
simulation when the Trellis structure parameter is
specified by using a workspace variable that contains the trellis structure as
opposed to calling the poly2trellis
function in the
Trellis structure parameter.
Use the Operation mode parameter to specify operating mode and the starting register states.
References
[1] Clark, George C., and J. Bibb Cain. ErrorCorrection Coding for Digital Communications. Applications of Communications Theory. New York: Plenum Press, 1981.
[2] Gitlin, Richard D., Jeremiah F. Hayes, and Stephen B. Weinstein. Data Communications Principles. Applications of Communications Theory. New York: Plenum Press, 1992.
[3] Yasuda, Y., K. Kashiki, and Y. Hirata. “HighRate Punctured Convolutional Codes for Soft Decision Viterbi Decoding.” IEEE^{®} Transactions on Communications 32, no. 3 (March 1984): 315–19. https://doi.org/10.1109/TCOM.1984.1096047.
[4] Haccoun, D., and G. Begin. “HighRate Punctured Convolutional Codes for Viterbi and Sequential Decoding.” IEEE Transactions on Communications 37, no. 11 (November 1989): 1113–25. https://doi.org/10.1109/26.46505.
[5] Begin, G., D. Haccoun, and C. Paquin. “Further Results on HighRate Punctured Convolutional Codes for Viterbi and Sequential Decoding.” IEEE Transactions on Communications 38, no. 11 (November 1990): 1922–28. https://doi.org/10.1109/26.61470.
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
Note
For an HDLoptimized convolutional encoder with hardwarefriendly control signals, use the Convolutional Encoder (Wireless HDL Toolbox) block. The Wireless HDL Toolbox™ block also simulates the latency of the HDL algorithm in Simulink.
HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic.
This block has one default HDL architecture.
ConstrainedOutputPipeline  Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is

InputPipeline  Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

OutputPipeline  Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

Input data requirements:
Must be scalar input
Must have a
boolean
orufix1
data type
HDL Coder supports only these coding rates:
½ to 1/7
2/3
HDL Coder supports only constraint lengths for 3 to 9.
Specify Trellis structure by the
poly2trellis
function.HDL Coder supports these Operation mode settings:
Continuous
Reset on nonzero input via port
If you select this mode, you must select the Delay reset action to next time step option. When you select this option, the Convolutional Encoder block finishes its current computation before executing a reset.
You cannot generate HDL for this block inside a Resettable Synchronous Subsystem (HDL Coder).
Version History
Introduced before R2006a
See Also
Blocks
Functions
Objects
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