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Generation of Clock Bundle Signals in HDL Coder

The clock bundle signals consist of clock, reset, and clock enable signals. During code generation, HDL Coder™ creates the clock bundle signals based on sequential elements such as persistent variables or Delay blocks that you use in your design. By default, a single master clock and a single master reset drives all sequential elements in your design.

MATLAB Code and Clock Relationship

If you use persistent variables in MATLAB®, HDL Coder generates the clock bundle signals. A persistent variable is a local variable in a MATLAB function that retains its value in memory between calls to the function. For code generation, functions must initialize a persistent variable if it is empty. For more information, see persistent.

Consider this MATLAB code that uses a persistent variable n.

function y = persist_fcn(u)
    persistent n
        
    if isempty(n)
        n = 1;
    end
    
    y = n;
    n = n + u; 
end

When you generate code, HDL Coder creates the clock, reset, and clock enable signals. These signals are named as clk, reset, and clk_enable in the HDL code. To learn how to generate HDL code, see Basic HDL Code Generation and FPGA Synthesis from MATLAB.

This code shows the generated Verilog code for the model. To match the MATLAB persistent variable behavior, the HDL code uses an always block. At the positive edge of the clock signal, when reset is low and the enable signal is high, the value tmp is assigned to the variable n after a delay of 1 ns.

`timescale 1 ns / 1 ns

module persist_fcn_fixpt
          (clk, reset, clk_enable,
           u, ce_out, y);

  input   clk, reset, clk_enable;
  input   u;  // ufix1
  output  ce_out;
  output  y;  // ufix1
..

assign enb = clk_enable;

assign p4tmp_1 = {1'b0, u};
assign tmp = n + p4tmp_1;

always @(posedge clk or posedge reset)
    begin : n_reg_process
      if (reset == 1'b1) begin
        n <= 2'b01;
      end
      else begin
        if (enb) begin
          n <= tmp;
        end
      end
    end

    assign y = n[0];
    assign ce_out = clk_enable;

endmodule  // persist_fcn_fixpt

See also Persistent Variables and Persistent Array Variables.

Simulink Model and Clock Relationship

To model sequential elements in Simulink® and generate the clock bundle signals, you can use various kinds of Delay blocks, Stateflow® charts, or persistent variables in MATLAB Function blocks or MATLAB System blocks. The code generator maps the sample time that you specify on your model to clock cycles in the HDL design. By default, a model is single rate which means that one sample time unit in Simulink maps to one clock cycle in the HDL code.

For example, consider this model that outputs unary minus of an input after two units of sample time. The input has int32 as the output data type.

Model that computes unary minus of input after two sample time units.

When you generate code, HDL Coder creates the clock, reset, and clock enable signals. These signals are named as clk, reset, and clk_enable in the HDL code. To learn how to generate code, see Generate HDL Code from Simulink Model.

This code shows the generated Verilog code for the model. To match the Simulink Delay block behavior, the HDL code uses an always block for each Delay block. At the positive edge of the clock signal, when reset is low and the enable signal is high, the input is passed to the output after a unit delay. One always block delays the input by 1 ns before computing the unary minus. The other always block computes the unary minus after 1 ns.

`timescale 1 ns / 1 ns

module unary_minus
          (clk, reset, clk_enable,
           In1, ce_out, Out1);

  input   clk, reset, clk_enable;
  input   signed [31:0] In1;  // int32
  output  ce_out;
  output  signed [31:0] Out1;  // int32
 ...

  assign enb = clk_enable;

  always @(posedge clk or posedge reset)
    begin : Delay_process
      if (reset == 1'b1) begin
        Delay_out1 <= 32'sb0;
      end
      else begin
        if (enb) begin
          Delay_out1 <= In1;
        end
      end
    end
 ...

  always @(posedge clk or posedge reset)
    begin : Delay2_process
       if (reset == 1'b1) begin
        Delay2_out1 <= 32'sb0;
      end
      else begin
        if (enb) begin
          Delay2_out1 <= Unary_Minus_out1;
        end
      end
    end 
 ...

endmodule  // unary_minus

If you use different sample times in your model or enable speed and area optimizations, the model becomes multirate. To learn about clock bundle generation from multirate models, see Code Generation from Multirate Models.

See Also

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