Repeating Sequence Stair

R2026b

Output and repeat discrete time sequence

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Repeating Sequence Stair block

To add a block to a model, double-click the canvas and start typing the block name. Then, select the block from the list.

Libraries:
Simulink / Sources

Description

The Repeating Sequence Stair block outputs and repeats a stair sequence that you specify with the Vector of output values parameter. For example, you can specify the vector as [3 1 2 4 1]'. A value in Vector of output values is output at each time interval, and then the sequence repeats.

Examples

Fixed-Point S-Functions: Product and Sum

How to exercise a custom C language S-function written to compute a fixed-point "product and sum" operation. To see the source code for the S-function, use the right-click context menu to select "Block Parameters". When the dialog box appears, press the Edit button.

(Fixed-Point Designer)

Fixed-Point Prelookup and Interpolation

Demonstrates some of the features of Prelookup and Interpolation Using Prelookup blocks.

(Fixed-Point Designer)

Ports

Output

Port_1 — Repeating discrete output signal

scalar

Output signal generated based on the values in the Vector of time values and Sample time parameters.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated

Parameters

Main

Vector of output values — Vector of output values

[3 1 4 2 1].' (default) | vector

Specify the vector containing values of the repeating stair sequence.

Programmatic Use

Block Parameter: OutValues

Type: character vector

Values: vector

Default: '[3 1 4 2 1].''

Sample time — Time interval between samples

-1 (default) | scalar

Specify the time interval between samples. To inherit the sample time, set this parameter to -1. See Specify Sample Time for more information.

Programmatic Use

Block Parameter: tsamp

Type: character vector

Values: scalar

Default: '-1'

Signal Attributes

Output minimum — Minimum output value for range checking

[] (default) | scalar

Lower value of the output range that the software checks.

The software uses the minimum to perform:

• Parameter range checking (see Specify Minimum and Maximum Values for Block Parameters) for some blocks.

• Simulation range checking (see Specify Signal Ranges and Enable Simulation Range Checking).

• Automatic scaling of fixed-point data types.

• Optimization of the code that you generate from the model. This optimization can remove algorithmic code and affect the results of some simulation modes such as SIL or external mode. For more information, see Optimize using the specified minimum and maximum values (Embedded Coder).

Tips

Output minimum does not saturate or clip the actual output signal. Use the Saturation block instead.

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

Parameter:	OutMin
Values:	'[]' (default) | scalar in quotes

Output maximum — Maximum output value for range checking

[] (default) | scalar

Upper value of the output range that the software checks.

The software uses the maximum value to perform:

• Parameter range checking (see Specify Minimum and Maximum Values for Block Parameters) for some blocks.

• Simulation range checking (see Specify Signal Ranges and Enable Simulation Range Checking).

• Automatic scaling of fixed-point data types.

• Optimization of the code that you generate from the model. This optimization can remove algorithmic code and affect the results of some simulation modes such as SIL or external mode. For more information, see Optimize using the specified minimum and maximum values (Embedded Coder).

Tips

Output maximum does not saturate or clip the actual output signal. Use the Saturation block instead.

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

Parameter:	OutMax
Values:	'[]' (default) | scalar in quotes

Output data type — Specify the output data type

double (default) | Inherit: Inherit via back propagation | single | int8 | int32 | uint32 | int64 | uint64 | fixdt(1,16,2^0,0) | <data type expression> | ...

Choose the data type for the output. The type can be inherited, specified directly, or expressed as a data type object such as Simulink.NumericType.

The Data Type Assistant helps you set data attributes. To use the Data Type Assistant, click . For more information, see Specify Data Types Using Data Type Assistant.

Programmatic Use

Block Parameter: OutDataTypeStr

Type: character vector

Values: 'Inherit: Inherit via back propagation' | 'double' | 'single' | 'int8' | 'uint8' | int16 | 'uint16' | 'int32' | 'uint32' | 'int64' | 'uint64' | fixdt(1,16,0) | fixdt(1,16,2^0,0) | fixdt(1,16,2^0,0) | '<data type expression>'

Default: 'double'

Lock output data type setting against changes by the fixed-point tools — Prevent fixed-point tools from overriding data types

off (default) | on

Select to lock the output data type setting of this block against changes by the Fixed-Point Tool and the Fixed-Point Advisor. For more information, see Use Lock Output Data Type Setting (Fixed-Point Designer).

Programmatic Use

Block Parameter: LockScale

Type: character vector

Values: 'off' | 'on'

Default: 'off'

Block Characteristics

Data Types	Boolean | double | enumerated | fixed point | integer | single
Direct Feedthrough	no
Multidimensional Signals	no
Variable-Size Signals	no
Zero-Crossing Detection	no

Programmatic Use: Add Block

To add the block programmatically, use the add_block function with one of these library block paths as the source.

"simulink/Sources/Repeating Sequence Stair"

Example: add_block("simulink/Sources/Repeating Sequence Stair","myModel/myBlock",MakeNameUnique="on")

For information about programmatic access to individual block parameters, see the Programmatic Use section of parameter descriptions on this page.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays in the design. Distributed pipelining does not redistribute these registers. The default value is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see OutputPipeline (HDL Coder).
SynthesisAttributes	Specifies the synthesis attributes for the blocks and block output signals in the model. The generated HDL code contains these attributes. For more information, see SynthesisAttributes (HDL Coder).

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a