SPICE PJFET

SPICE-compatible P-Channel JFET

Libraries:
Simscape / Electrical / Additional Components / SPICE Semiconductors

Description

The SPICE PJFET block represents a SPICE-compatible P-channel junction field-effect transistor (PJFET). If the voltage applied to the gate port, gx, is greater than the voltage applied to the source port, sx, the current between the source port and drain port, dx, is reduced.

SPICE, or Simulation Program with Integrated Circuit Emphasis, is a simulation tool for electronic circuits. You can convert some SPICE subcircuits into equivalent Simscape™ Electrical™ models using the Environment Parameters block and SPICE-compatible blocks from the Additional Components library. For more information, see subcircuit2ssc.

Equations

Variables for the SPICE PJFET block equations include:

Variables that you define by specifying parameters for the SPICE PJFET block. The visibility of some of the parameters depends on the value that you set for other parameters. For more information, see Parameters.
Geometry-adjusted variables, which depend on several of the values that you specify using parameters for the SPICE PJFET block. For more information, see Geometry-Adjusted Variables.
Temperature, T, which is 300.15 K by default. You can use a different value by specifying parameters for the SPICE PJFET block or by specifying parameters for both the SPICE PJFET block and an Environment Parameters block. For more information, see Transistor Temperature.
Temperature-dependent variables. For more information, see Temperature Dependence.
Minimal conductance, GMIN, which is 1e-12 1/Ohm by default. You can use a different value by specifying a parameter for an Environment Parameters block. For more information, see Minimal Conduction.

Geometry-Adjusted Variables

Several variables in the equations for the P-channel junction field-effect transistor model consider the geometry of the device that the block represents. These geometry-adjusted variables depend on variables that you define by specifying SPICE PJFET block parameters. The geometry-adjusted variables depend on these variables:

AREA — Area of the device
SCALE — Number of parallel connected devices
The associated unadjusted variable

The table includes the geometry-adjusted variables and the defining equations.

Variable	Description	Equation
BETA_d	Geometry-adjusted transconductance	$B E T A_{d} = B E T A * A R E A * S C A L E$
CGD_d	Geometry-adjusted zero-bias gate-drain capacitance	$C G D_{d} = C G D * A R E A * S C A L E$
CGS_d	Geometry-adjusted zero-bias gate-source capacitance	$C G S_{d} = C G S * A R E A * S C A L E$
IS_d	Geometry-adjusted saturation current	$I S_{d} = I S * A R E A * S C A L E$
RS_d	Geometry-adjusted source resistance	$R S_{d} = \frac{R S}{A R E A * S C A L E}$
RD_d	Geometry-adjusted drain resistance	$R D_{d} = \frac{R D}{A R E A * S C A L E}$

Transistor Temperature

You can use these options to define transistor temperature, T:

Fixed temperature — The block uses a temperature that is independent of the circuit temperature when the Model temperature dependence using parameter in the Temperature settings of the SPICE PJFET block is set to Fixed temperature. For this model, the block sets T equal to TFIXED.
Device temperature — The block uses a temperature that depends on circuit temperature when the Model temperature dependence using parameter in the Temperature settings of the SPICE PJFET block is set to Device temperature. For this model, the block defines temperature as

$T = T_{C} + T O F F S E T$
Where:
- T_C is the circuit temperature.
  If there is not an Environment Parameters block in the circuit, T_C is equal to 300.15 K.
  If there is an Environment Parameters block in the circuit, T_C is equal to the value that you specify for the Temperature parameter in the SPICE settings of the Environment Parameters block. The default value for the Temperature parameter is 300.15 K.
- TOFFSET is the offset local circuit temperature.

Minimal Conduction

Minimal conductance, GMIN, has a default value of 1e–12 1/Ohm. To specify a different value:

If there is not an Environment Parameters block in the transistor circuit, add one.
In the SPICE settings of the Environment Parameters block, specify the desired GMIN value for the GMIN parameter.

Source-Gate Current-Voltage Model

This table shows the equations that define the relationship between the source-gate current, I_sg, and the source-gate voltage, V_sg. As applicable, the model parameters are first adjusted for temperature. For more information, see Temperature Dependence.

Applicable Range of V_sg Values	Corresponding I_sg Equation
$V_{s g} > 80 * V_{t}$	$I_{s g} = I S_{d} * ((\frac{V_{s g}}{V_{t}} - 79) e^{80} - 1) + V_{s g} * G \min$
$80 * V_{t} \geq V_{s g}$	$I_{s g} = I S_{d} * (e^{V_{s g} / V_{t}} - 1) + V_{s g} * G \min$

Where:

IS_d is the geometry-adjusted saturation current.
V_t is the thermal voltage, such that $V_{t} = N D * k * T / q$ .
ND is the emission coefficient.
q is the elementary charge on an electron.
k is the Boltzmann constant.
T is the transistor temperature. For more information, see Transistor Temperature
GMIN is the transistor minimum conductance. or more information, see Minimal Conduction

Drain-Gate Current-Voltage Model

This table shows the relationship between the drain-gate current, I_dg, and the drain-gate voltage, V_dg. As applicable, model parameters are first adjusted for temperature.

Applicable Range of V_dg Values	Corresponding I_dg Equation
$V_{d g} > 80 * V_{t}$	$I_{d g} = I S_{d} * ((\frac{V_{d g}}{V_{t}} - 79) e^{80} - 1) + V_{d g} * G \min$
$80 * V_{t} \geq V_{d g}$	$I_{d g} = I S_{d} * (e^{V_{d g} / V_{t}} - 1) + V_{d g} * G \min$

Source-Drain Current-Voltage Model

This table shows the relationship between the source-drain current, I_sd, and the source-drain voltage, V_sd, in normal mode (V_sd ≥ 0). As applicable, model parameters are first adjusted for temperature.

Applicable Range of V_sg and V_dg Values	Corresponding I_sd Equation
$V_{s g} - V_{t o} \leq 0$	$I_{s d} = 0$
$0 < V_{s g} - V_{t o} \leq V_{s d}$	$I_{s d} = β_{d} {(V_{s g} - V_{t o})}^{2} (1 + λ V_{s d})$
$0 < V_{s d} < V_{s g} - V_{t o}$	$I_{s d} = β_{d} V_{s d} (2 (V_{s g} - V_{t o}) - V_{s d}) (1 + λ V_{s d})$

Where:

V_to is the threshold voltage.
β_d is the geometry-adjusted transconductance.
λ is the channel modulation.

This table shows the relationship between the source-drain current, I_sd, and the source-drain voltage, V_sd, in inverse mode (V_sd < 0). As applicable, model parameters are first adjusted for temperature.

Applicable Range of V_sggs and V_dg Values	Corresponding I_sd Equation
$V_{d g} - V_{t o} \leq 0$	$I_{s d} = 0$
$0 < V_{d g} - V_{t o} \leq - V_{s d}$	$I_{s d} = - β_{d} {(V_{d g} - V_{t o})}^{2} (1 - λ V_{s d})$
$0 < - V_{s d} < V_{d g} - V_{t o}$	$I_{s d} = β_{d} V_{s d} (2 (V_{d g} - V_{t o}) + V_{s d}) (1 - λ V_{s d})$

Junction Charge Model

This table shows the relationship between the source-gate charge, Q_sg, and the source-gate voltage, V_sg. As applicable, model parameters are first adjusted for temperature.

Applicable Range of V_sg Values	Corresponding Q_sg Equation
$V_{s g} < F C * V J$	$Q_{s g} = \frac{C G S_{d} * V J * (1 - {(1 - \frac{V_{s g}}{V J})}^{1 - M G})}{1 - M G}$
$V_{s g} \geq F C * V J$	$Q_{s g} = C G S_{d} * (F 1 + \frac{F 3 * (V_{s}_{g} - F C * V J) + \frac{M G * (V_{s g}^{2} - {(F C * V J)}^{2})}{2 * V J}}{F 2})$

Where:

FC is the capacitance coefficient.
VJ is the junction potential.
CGS_d is the zero-bias gate-source capacitance.
MG is the grading coefficient.
$F 1 = \frac{V J * (1 - {(1 - F C)}^{1 - M G})}{1 - M G}$
$F 2 = {(1 - F C)}^{1 + M G}$
$F 3 = 1 - F C * (1 + M G)$

This table shows the relationship between the drain-gate charge, Q_dg, and the drain-gate voltage, V_dg. As applicable, model parameters are first adjusted for temperature.

Applicable Range of V_dg Values	Corresponding Q_dg Equation
$V_{d g} < F C * V J$	$Q_{d g} = \frac{C G D_{d} * V J * (1 - {(1 - \frac{V_{d g}}{V J})}^{1 - M G})}{1 - M G}$
$V_{d g} \geq F C * V J$	$Q_{d g} = C G D_{d} * (F 1 + \frac{F 3 * (V_{d g} - F C * V J) + \frac{M G * (V_{d g}^{2} - {(F C * V J)}^{2})}{2 * V J}}{F 2})$

Where:

CGD_d is the geometry-adjusted zero-bias gate-drain capacitance.

Temperature Dependence

The block provides this relationship between the saturation current IS and the transistor temperature T:

$I S (T) = I S_{d} * {(T / T_{m e a s})}^{\frac{X T I}{N D}} * e^{(\frac{T}{T_{m e a s}} - 1) * \frac{E G}{V_{t}}}$

Where:

IS_d is the geometry-adjusted saturation current.
T_meas is the parameter extraction temperature.
XTI is the saturation current temperature exponent.
EG is the energy gap.
V_t is the thermal voltage, such that $V_{t} = N D * k * T / q$ .
ND is the emission coefficient.

The relationship between the junction potential, VJ, and the transistor temperature T is

$V J (T) = V J * (\frac{T}{T_{m e a s}}) - \frac{3 * k * T}{q} * \log (\frac{T}{T_{m e a s}}) - (\frac{T}{T_{m e a s}}) * E G_{T_{m e a s}} + E G_{T}$

Where:

VJ is the junction potential.
$E G_{T_{m e a s}} = 1.16 e V - (7.02 e - 4 * T_{m e a s}^{2}) / (T_{m e a s} + 1108)$
$E G_{T} = 1.16 e V - (7.02 e - 4 * T^{2}) / (T + 1108)$

The relationship between the gate-source junction capacitance, CGS, and the transistor temperature, T:

$C G S (T) = C G S_{d} * [1 + M G * (400 e - 6 * (T - T_{m e a s}) - \frac{V J (T) - V J}{V J})]$

Where:

CGS_d is the geometry-adjusted zero-bias gate-source capacitance.

The block uses the CGS(T) equation to calculate the gate-drain junction capacitance by substituting CGD_d, the zero-bias gate-drain capacitance, for CGS_d.

The relationship between the transconductance, β, and the transistor temperature T is

$β (T) = β_{d} * (\frac{T}{T_{m e a s}})$

Where β_d is the geometry-adjusted transconductance.

Assumptions and Limitations

The block does not support noise analysis.
The block applies initial conditions across junction capacitors and not across the block ports.

Ports

Conserving

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gx — Gate terminal
electrical

Electrical conserving port associated with the transistor gate terminal.

dx — Drain terminal
electrical

Electrical conserving port associated with the transistor drain terminal.

sx — Source terminal
electrical

Electrical conserving port associated with the transistor source terminal.

Parameters

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Main

Device area, AREA — Device area
`1.0` `m^2` (default) | positive scalar

Transistor area. The value must be greater than 0.

Number of parallel devices, SCALE — Number of parallel devices
`1` (default) | positive integer

Number of parallel transistors the block represents. The value must be an integer greater than 0.

Threshold voltage, VTO — Threshold voltage
`-2` `V` (default) | scalar

Source-gate voltage above which the transistor produces a nonzero drain current.

Transconductance, BETA — Channel modulation
`1e-4` `A/m^2/V^2` (default) | nonnegative scalar

Derivative of drain current with respect to gate voltage. The value must be greater than or equal to 0.

Channel modulation, LAMBDA — Channel modulation
`0` `1/V` (default) | scalar

Channel modulation.

Saturation current, IS — Saturation current
`1e-14` `A/m^2` (default) | nonnegative scalar

Magnitude of the current that the gate-current equation approaches asymptotically for very large reverse bias levels. The value must be greater than or equal to 0.

Drain resistance, RD — Series resistance
`0.01` `m^2*Ohm` (default) | nonnegative scalar

Transistor drain resistance. The value must be greater than or equal to 0.

Source resistance, RS — Series resistance
`0.0001` `m^2*Ohm` (default) | nonnegative scalar

Transistor source resistance. The value must be greater than or equal to 0.

Emission coefficient, N — Emission coefficient
`1` (default) | positive scalar

Transistor emission coefficient or ideality factor. The value must be greater than 0.

Junction Capacitance

Model junction capacitance — Junction capacitance model
`No` (default) | `Yes`

Options for modeling the junction capacitance:

No — Do not include junction capacitance in the model.
Yes — Specify zero-bias junction capacitance, junction potential, grading coefficient, forward-bias depletion capacitance coefficient, and transit time.

Dependencies

Selecting Yes exposes related parameters.

Zero-bias GS capacitance, CGS — Zero-bias junction capacitance
`0` `F/m^2` (default) | nonnegative scalar

Value of the capacitance placed between the gate and the source. The value must be greater than or equal to 0.