Reducing area utilization in HDL code

Hi,

I am currently working on a project to implement 16 QAM modulator in FPGA. I was using simulink model for functional simulation and generated code using HDL coder.When the above mentioned code was synthesized for ARTIX 7 FPGA the resource utilization report showed a high number of LUTs and the design could not be accomodated in FPGA. Please suggest me some way to optimize code generation or to reduce number of LUTs used.

Krishnakumar

Answer 1

[Girish Venkataramani]

There are several resource sharing features you can try out. If you look at the HDL Coder product examples in the doc, you'll find a section optimizations. 'Sharing' and 'Streaming' are two common ways to reduce area footprint. You can share multipliers that are identical or entire Simulink subsystems if they are identical. In the latter case, the subsystems must be marked as non-virtual, atomic subsystems.

[Krishnakumar]

Sir,

       Thank You for your answer.I would also like to know how can we reduce the number of DSP48E1 slices used when we generate code automatically using HDL coder.

Krishnakumar

[Girish Venkataramani]

Typically a DSP48 represents a multiplier usage on the FPGA. If your design has a lot of product/gain Simulink blocks or multiply operations in MATLAB, it will use up a lot of DSP48 slices.

As I said in my last answer, if you are using several product/gain blocks in the same subsystem, you can use SharingFactor to reduce the multiplier usage by sharing.

If you are using a lot of gain blocks, you can use the CSD/FCSD optimizations that can be turned on through the Gain block's HDL properties.

Hope this helps.