ERROR DETECTION USING STANDARD FCS ALGORITHM

AT THE GENERATOR:-

INPUT 1:- (k bit) message pattern of 0's and 1's as a line of ASCII text.

INPUT 2:- (n+1 bit) generator pattern of 0's and 1's also in ASCII .

1] Now firstly according to FCS algorithm; we have to pad n zeroes to the k-bit message pattern. For example if our original message pattern is of 4 bits (k=4) i.e 1100 and generator pattern is of 4 bits (n+1=4) i.e. 1101; then we have to pad 3 zeroes (as n=3) to our original message pattern.

So our " NEW MESSAGE PATTERN":- 1100 000 (k+n bits)

2] Now we have to perform XOR division of this new message pattern and our Generator pattern.

So summarizing we need to perform XOR Division of our " NEW MASSAGE PATTERN " ; (now consisting of k-bit message and n-zeroes) and " Generator Pattern " (n+1 bits) .

3] In the remainder we obtain n- FCS bits which we replace by the n-zeroes of the " NEW MESSAGE PATTERN " to obtain the final TRANSMITTED PATTERN at the generator.

The OUTPUT should be a standard output line of ASCII text with " k+n " 0's and 1's representing the message to be transmitted (including the original k-bit message + the n-bit FCS bits).

Also represent the TRANSMITTED PATTERN in a Polynomial form.

I have solved a problem which can also be referred to in the attached flyer.

[Geoff Hayes]

Garry - please clarify what your question is (if one exists).

[garry]

Okay.. I tried to explain the procedure above.

This is the exact question Geoff:-

----> Implement an error detection mechanism using the standard FCS algorithm Write two programs, call them "Generator" and "Verifier".

---> The Generator program reads from a standard input a "k-bit" message as a string of "0s and 1's" as a line of ASCII text. The generator program also reads from a second line a "(n+1)-bit" generator pattern also in ASCII. The Generator program outputs to a standard output a line of ASCII text with "k+n" 0's and 1's representing the message to be transmitted (including the original k-bit message + the n-bit FCS bits). It also outputs the polynomial (just as it reads it in).

---> The Verifier program reads in the output of the Generator program and outputs a message indicating whether it is correct or not.

---> Finally, write a program "Alter" that inverts one bit on the first line (assume that that the leftmost bit position is #1) but copies the rest of the two lines correctly. The output of this program should indicate whether the error is detected or not.

[M H]

:D

[garry]

heyyy "M H"...

Did u try the code in matlab..??

I could understand the Code partially in java.