Sampling Time and oscillator

I have this system that it is sampled at every 2 us. It is a model that represent a FPGA implementation (which sampling time is 8ns). 2us was selected to speed up the simulation process. The model has got an oscillator that generates a ramp with period of (60*12)^(-1), where 60 is the AC frequency, and with a final peak value of 50/60, see below the ramp generated by the oscillator

This oscillator is supposed to intercept the point =50/60 at the end of its period ( = 1388.88 us), but this number is not multiple of the sampling frequency (2us) which then results in a small error that is amplified later in the system.

What Can I do in this case?. (so as to avoid this un-sync of the oscilaltor ramp and the clock frequency)

Thanks in advance for your comments

Answer 1

[William Rose]

@Ismael Ochoa,

"What Can I do in this case?"

1. You can ignore the small variation in the peak heights. Does it matter?
2. You can choose a sampling frequency that is an integer multiple of the ramp frequency. The ramp frequency is 1200 Hz, and your sampling rate is 500 KHz. For example, you could use a sampling rate of 480 KHz (), or 500.4 KHz (), etc. The sample y-values at the corners may not be exactly 0 and 5/6, depending on the phase angle of the sampling, relative to the phase angle of the sawtooth, but the y-values will all be the same, if you do that.

Good luck with your work.