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Simulink HDL Coder equivalent to attribute synthesis off?

6 vues (au cours des 30 derniers jours)
Martin Ryba
Martin Ryba le 14 Juin 2023
Modifié(e) : Kiran Kintali le 19 Juin 2023
I have a DSP-heavy block that I've created targeting a Xilinx FPGA core. Embedded within a submodule are some debug/visualization outputs that are handy when running the model (e.g., a constellation diagram for a demodulator). It would be handy if there was something akin to the VHDL attribute synthesis on/off (or its Verilog equivalent) where one can mark bits of code for use in modeling but not for synthesis, since clearly I can't synthesize a constellation plot. Short of commenting the blocks out (and then uncommenting when I want to run the model again), or bringing all that debug stuff to the top level "test bench" so I can mark just the core for HDL Coder, is there any way to assign a conditional commenting-out for HDL Coder?
  1 commentaire
Kiran Kintali
Kiran Kintali le 19 Juin 2023
Modifié(e) : Kiran Kintali le 19 Juin 2023
Unfortunately, HDL Coder currently does not have this support; this request is actively under consideration from the development team.
The current proposal under consideration is being able to pull the debug logic into a subsystem and specify a pragma at the subsystem level to turn off the logic using VHDL attribute synthesis on/off.
Feel free to reach out to me directly or tech support for any followups on this topic in our upcoming R2023b release.

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Réponses (1)

Satwik le 14 Juin 2023
Yes, HDL Coder provides a mechanism for including or excluding code regions from synthesis using pragmas. Pragmas are special annotations that you can add to the source code to give hints or directives to the synthesis tool. One of the pragmas supported by HDL Coder is `#define`, which can be used to define preprocessor macros that control whether certain code regions are included or excluded from synthesis.
Here's an example of how you could use `#define` to conditionally exclude code regions:
% Define a preprocessor macro that controls whether to include debug code
% Conditionally include the debug code if the macro is defined
disp('Debug output enabled');
% Code to generate constellation diagram goes here
disp('Debug output disabled');
In this example, we define a preprocessor macro called `DEBUG_ENABLED` that is used to conditionally include or exclude the debug code. If the macro is defined (e.g., if `#define DEBUG_ENABLED` is present in the code), then the `disp` and debug code will be included in the synthesis. If the macro is not defined, then the `#ifdef` block will be skipped during synthesis.
To enable or disable the debug code, you can simply modify the `#define` statement at the top of the file as needed. This provides a convenient way to toggle the inclusion of the debug code without having to modify the actual code itself.
  1 commentaire
Martin Ryba
Martin Ryba le 14 Juin 2023
How does this work for a Simulink model? What you showed appears to be an option for MATLAB code to be run in HDL Coder. Or am I missing something?

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