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Kiran Kintali


Last seen: 3 jours ago

MathWorks

419 total contributions since 2011

Professional Interests: Signal Processing, FPGAs and ESL Design

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Answered
HDL synthesis doen't end?
It is possible you have very high resource usage or timing issue with your generated code. You should consider using high leve...

17 jours ago | 0

Answered
How can I force HDL Coder to use DSP48 slices?
if you are looking to automate DSP usage improvements you can consider using Adaptive pipelining optimization in HDL Coder. Ada...

18 jours ago | 0

Answered
How to update template on multiple Simulink models (programmatically)?
https://www.mathworks.com/help/hdlcoder/ug/hdl-coder-simulink-templates.html Use Simulink Templates for HDL Code Generation HD...

20 jours ago | 0

Answered
IP core generation zedboard FMCOMMS2 gives 2 critical warning in Vivado
web(fullfile(docroot, 'hdlcoder/ug/hdlqpsktransmitterandreceiver.html?s_tid=doc_srchtitle'))

20 jours ago | 0

Answered
Can I use a IFFT HDL Optimized block with an input length greater than 2^16?
https://www.mathworks.com/help/dsp/ref/dsp.hdlfft-system-object.html FFT length — Number of data points used for one FFT calcul...

20 jours ago | 0

Answered
Issues: FIR filter by HDL Coder on Redpitaya platform
>> mlhdlc_demo_setup('sfir')

20 jours ago | 0

Answered
Problems occur when both simulink HDL blocks and vivado HLS blocks are used to generate HDL code.
https://www.mathworks.com/help/hdlcoder/ug/using-xilinx-system-generator-for-dsp-with-hdl-coder.html

20 jours ago | 0

Answered
results of HDL streaming FFT block is not same as FFt block in dsp toolbox
dsp.HDLFFT is optimized for HDL Code generation. dsp.HDLFFT Fast Fourier transform — optimized for HDL code generation The H...

20 jours ago | 0

Answered
Potential Bugs in R2014b HDL Coder ('hdlcoder_slsysgen')
https://www.mathworks.com/help/hdlcoder/ug/using-xilinx-system-generator-for-dsp-with-hdl-coder.html

20 jours ago | 0

Answered
Generating higher sampling frequency
Using Oversampling Factor and Latency Strategy The Oversampling factor (HDL Coder) specifies the factor by which the FPGA clock...

20 jours ago | 0

Answered
GPU: Audio DSP
https://www.mathworks.com/help/hdlcoder/ug/running-an-audio-filter-on-live-audio-input-using-a-zynq-board.html

20 jours ago | 0

| accepted

Answered
Can Matlab R2018b use the Kintex7 board from a X310 USRP and, if so, how?
https://www.mathworks.com/hardware-support/usrp.html

20 jours ago | 0

Answered
FPGA: Audio DSP
Running an Audio Filter on Live Audio Input Using a Zynq Board This example shows how to model an audio system and implement it...

20 jours ago | 0

| accepted

Answered
Error while converting a sine PWM block in simulink to HDL code
See the attached example on how to generate square wave pulses at regular intervals. The waveform parameters, Amplitude, Pulse W...

20 jours ago | 0

Answered
Having issues with connecting Zynq zedboard to computer
web(fullfile(docroot, 'hdlcoder/ug/define-and-register-custom-board-and-reference-design-for-zynq-workflow.html'))

20 jours ago | 0

Answered
I want to know about the resource utilization on a FPGA when using FFT HDL code generated by HDL coder application on MATLAB.
web(fullfile(docroot, 'dsp/ref/ffthdloptimized.html?s_tid=doc_ta')) Check Performance section

20 jours ago | 0

Answered
How does it work the AXI4 Stream IIO driver?
web(fullfile(docroot, 'hdlcoder/ug/getting-started-with-axi4-stream-interface-in-zynq-workflow.html?s_tid=doc_srchtitle')) we...

20 jours ago | 0

Answered
Best Practices for Simulink HDL Coder Development
https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-guide HDL Coder Evaluation Referenc...

20 jours ago | 0

Answered
HDL Coder (2014b) fixed point division RoundMode error
Consider using hdlfimath when generating HDL code from MATLAB with fixed-point. >> hdlfimath

20 jours ago | 0

Answered
Does HDL coder from Simulink support AXI-4 Stream Interface for Xilinx Zynq?
Getting Started with AXI4-Stream Interface in Zynq Workflow This example uses: HDL Coder DSP System Toolbox Embedded Coder...

20 jours ago | 0

Answered
Strange behavior of HDL coder when generating resettable register
Synchronous Subsystem Behavior with the State Control Block What Is a State Control Block? When you have blocks with state, ...

20 jours ago | 0

Answered
I have the following errors when I run HDL coder in MATLAB 2013a ?errors in fixed point conversion
This is an unexpected internal error during fixed-point conversion. The issue occurs during verification step of generated fixed...

20 jours ago | 0

Answered
How to prepare FPGA board for MATLAB
You would need license to HDL Coder. See third party tool requirements for HDL Coder in this page. web(fullfile(docroot, 'hdlc...

20 jours ago | 0

Answered
Is it possible to purge Simulink Model?
attached sample file can be extended to purge whatever cruft you have in your session. >> purgesession Purging slprj Purging ...

20 jours ago | 0

Answered
Simulation of matlab generated vhdl code leads to Errors
HDL Coder handles MATLAB one based indexing and converts the logic to zero based indexing when generating VHDL / Verilog code. ...

20 jours ago | 0

Answered
HDL Coder with Xilinx Sysgen R2013b
Using Xilinx® System Generator for DSP with HDL Coder™ This example shows how to use Xilinx System Generator for DSP with HDL C...

20 jours ago | 0

Answered
sir I want to convert my .m file to VHDL . my code is given below.
You need to break the design into two parts. A testbench and a design. Follow basic example shown here. >> mlhdlc_demo_setup('...

22 jours ago | 0

Answered
How to do area optimization(sharing and streaming) with feedback loop like that AGC or AFC in communication system?
To address pipelining of blocks in feedback loops you can refer to this example and related HDL Coder features. https://www.mat...

22 jours ago | 0

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