Sampling rate issue while working on ADRV9361-Z7035 using Software/Hardware co-design workflow

Sir,

We are using ADRV9361-Z7035 as a SDR development platform using MATLAB/Simulink H/W S/W Co-design apparaoch. We generated IP core which is a multi-rate system and the base rate is 640 ksps. The system sampling rate is downsampled by 16 at the later stage in the generated IP core to get the output sampling rate at 40 ksps. However, when the software interface model is build and deployed on ARM, the output sampling rate isn't 40 ksps. I am getting the I/Q data at the sampling rate of 640 ksps at the PL-PS boundary (which is transferred using DMA Rx I1/Q1) out interface. Is it possible to change the sampling rate to the required value at this interface. Our requirement is to get the sampling rate at ARM Processor 40 ksps.

[Rahul Barnwal]

Hi,

Can you please let me know how to port H/W S/W Co-design QPSK example to ADRV9361-Z7035.

Thanks in advance

Answer 1

[recent works]

It sounds like you have designed a multi-rate system in MATLAB/Simulink using the Hardware/Software co-design approach for the ADRV9361-Z7035 platform. The IP core you generated performs downsampling to achieve an output sampling rate of 40 ksps. However, when running the software interface model on the ARM processor, you are still getting data at 640 ksps at the PL-PS boundary.

The issue you are facing is likely due to a mismatch in the data processing configuration between the IP core and the software running on the ARM processor. Here are a few things to check and consider:

1. Verify IP core settings: Double-check the configuration of the IP core in your hardware design. Ensure that the downsampling factor is correctly set to achieve the desired output sampling rate of 40 ksps.
2. Interface communication: Ensure that the data transfer between the IP core and the ARM processor is set up correctly. The interface should be configured to handle data at the desired output rate (40 ksps).
3. DMA settings: Review the Direct Memory Access (DMA) settings used to transfer data between the PL (Programmable Logic) and PS (Processing System) in the Zynq SoC. Make sure that the DMA settings align with the desired sampling rate.
4. Clocking and timing: Check the clocking and timing settings in both the IP core and the ARM processor software. The system should be synchronized to handle data at the desired rate.
5. Data processing on ARM: Verify the data processing and buffering on the ARM side. Ensure that the ARM processor is processing the received data at the correct rate (40 ksps) after it has been transferred via DMA.
6. Software algorithm: Review the algorithm and code running on the ARM processor to ensure that it can process data at the target rate.

If all the above steps are correct and you are still experiencing issues, it's possible that there might be a configuration or software bug in your system. Debugging such complex systems can be challenging, and you may need to use debugging tools and techniques specific to the ADRV9361-Z7035 platform and the co-design environment.

[Jitendra]

Thank You Recent Works,

I will try all these steps as mentioned by you and let you know the result.