Why do I receive sample time error when assigning bus element in a constant virtual bus, when trying to compile an FMU?

I am getting a sample time error when trying to compile a FMU from a simulink model in which I assign signals in a bus (inf sample time) with signals from other sample times.

Above is the rough setup I would like to use (typically part of a proper, larger model). I have used this pattern in previous projects for the last two years and this error never occured. I looked at the past projects, but didn't find any obvious differences which should produce this error now.

I figured that setting all inputs to the bus assignment block resolves the issue:

However this is very inconvenient, as our bus structures get pretty big, and taking care of all sample times for all Constant signals assigned is quite some extra work (especially since it successfully worked before without matching all sample times).

Setting only one of the constants to the proper sample times does not work either:

Especially in this case, where the bus has the "correc" sample time, I would expect simulink to be fine with it.

Note: I have tried the 3 different settings for "Automatically handle rate transition for data transfer" and they do not chang the results of this.

But there is an easy "fix" for this problem:

If I connect an outport block to the not-rate-trasitioned-signal, it works again and gets compiled.

In fact, this works in the bigger model as well, but obviously I do not want to output an unnecessary amount of large bus structures.

Can someone explain me what the underlying issue is here and why it is solved by adding the output port?

Furthermore: How can I keep my original pattern (first picture, with no sample times set in the constant blocks)? This would make development a lot easier, than setting the sample times in all the constant blocks.

[Brahmadev]

Hi, could you share your model so that the error can be reproduced better?

[Daniel Eberle]

I attached a zip file containing the example above (with renamed bus objects).

Note: I seem to have "found" the issue.

When I switched the default parameter beavior for code generation from tunable to inlined, the error did not occur.

However it would be nice to understand why this "solves" the problem, as this seems rather unintuivite...

Answer 1

[Lucian]

I had a similar problem.

In my case the fix was to change the sample time of the constant blocks from inf to -1