How to receive the correct output which is 5 level for Cascaded H-Bridge Inverter using IGBT with different input voltage?

This circuit is to simulate to get 5 level h bridge inverter level with different input voltage using 10V and 20V. The problem is do not get the correct output (staircase). Below coding explains the declaration of pulse width and phase delay for the pulse generator.

f =50;

T = 1/f;

Tp = 0;

Tn = (T/2) ;

%converter 1

DZ1=(20.4/360)*100;

DZ3=(20.4/360)*100;

DZ7=(20.4/360)*100;

DZ8=(20.4/360)*100;

DZ2 = (67.2/360)*100;

DZ4 = (26.4/360)*100;

DZ5 = (26.4/360)*100;

DZ6= (120/360)*100;

tAp1= (9.6/360)*0.02;

tAn1= Tn + tAp1;

tAp4 = (30/360)*0.02;

tAn4 = Tn + tAp4;

tAp2 = (56.4/360)*0.02;

tAn2 = Tn + tAp2;

% DZ5 = (26.4/360)*100;

tAp5 = (123.6/360)*0.02;

tAn5 = Tn + tAp5;

% DZ3 = (20.4/360)*100;

tAp3 = (150/360)*0.02;

tAn3 = Tn + tAp3;

% converter2

% DZ6= DZ4+DZ5+DZ6;

tAp6= (30/360)*0.02;

tAn6 = Tn + tAp6;

% DZ7 = DZ1;

tAp7 = (9.6/360)*0.02;

tAn7 = Tn + tAp7;

% DZ8 = DZ3;

tAp8= (150/360)*0.02;

tAn8 = Tn + tAp8;

Answer 1

[Sayan]

Hi Sarah,

I have investigated the model. There are some connection and parameter issues in your model.

• The two H-bridge inverters are not connected in cascade.
• You are not using snubber (i.e., Snubber resistance = 0 and Snubber capacitance = inf) which results in no parallel path with the "IGBT". This causes an open circuit error in the circuit when all the switches are open.

However, after fixing the above issues, I could run the circuit, but only 3 levels were obtained, i.e., 0, 30, and 30. I have attached a model named "H_5_9_modified.slx" herewith. The reason for only 3 levels is that both inverter circuits are on at the same time. For 5 levels, i.e., 0, 10, 30, -10, and -30, the voltage levels 10 and -10 need to be obtained. These can be done with the two following switching patterns:.

• On state gate pulses: Inverter 1 -> S1A & S1A2 Inverter 2 -> S1B & S3B. This will turn on S1, S2, S5, and S7. This will give a +10 voltage level.
• On state gate pulses: Inverter 1 -> S1A3 & S1A1 Inverter 2 -> S2B & S4B. This will turn on S1, S2, S6, and S8. This will give a voltage level of -10.

But this switching pattern is not there in your model switching pulses. It can be found in the following screenshot.

However, an alternative to this is using reverse diodes with the IGBT or using the "IGBT/DIODE" block (available at Simscape / Electrical / Specialized Power Systems / Power Electronics). The reverse diode helps get the extra voltage levels in the output voltage. I am attaching another model named "H_5_9_IGBTDiode.slx" which implements the inverter circuit for the "IGBT/DIODE" switches. I have obtained 7 levels of voltage, i.e., 0, 10, 20, 30, -10, -20, and -30 with this.

A level shifted PWM technique has been used in the following model in File Exchange. You may find this useful.

https://www.mathworks.com/matlabcentral/fileexchange/122517-cascaded-h-bridge-five-level-inverter

Hope this helps in resolving the issue.