how to use local parameter in HDL Coder toolbox?

Dear MATLAB Support Team,

I am currently working on developing an UART transmitter block in Simulink. Within this block, I require two parameters: CLOCK_FREQ and BAUD_RATE, which are essential for calculating the DIVIDER parameter, given by CLOCK_FREQ / BAUD_RATE.

While I have learned how to generate parameters using HDL Coder, I am facing confusion regarding the generation of the local parameter DIVIDER, which will be utilized within a counter block. I aim to produce Verilog code similar to the following:

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parameter BAUD_RATE = 9600;

parameter CLOCK_FREQ = 100000000;

localparam DIVIDER = CLOCK_FREQ / BAUD_RATE;

if (clk_divider == DIVIDER) begin

// Further implementation

end

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However, the generated code I am obtaining differs:

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parameter integer BAUD_RATE = 9600;

parameter integer CLOCK_FREQ = 100000000;

assign DIVIDER_out1 = 32'b00000000000000000010100010110001;

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How can I use BAUD_RATE and CLOCK_FREQ within the module to generate other parameters?

The Constant Block setting is as follows:

Answer 1

[kiyoko]

Unfortunately, HDL Coder does not support the generation of "localparam". "Generate Parameterized HDL Code for Constant and Gain Blocks" is only compatible with "parameter".

As an alternative, if you have custom HDL code, you can use the DocBlock block to integrate that custom HDL code into your design.

[SHIYU SONG]

Hi, kiyoko

Thank you for your answer!

In the scenario above, how can I use the two parameters CLOCK_FREQ and BAUD_RATE?

In Simulink, any operation on these two parameters will appear as a module, such as the division implementation DIVIDER = CLOCK_FREQ / BAUD_RATE;

However, in reality, the values of CLOCK_FREQ and BAUD_RATE will be determined at compile time, without the need to calculate the specific value of DIVIDER = CLOCK_FREQ / BAUD_RATE during FPGA operation, which would introduce delays and consume resources.