Access FPGA External Memory Using AXI Manager over PCI Express Implement

I tried to follow the example:

Access FPGA External Memory Using AXI Manager over PCI Express - MATLAB & Simulink Example (mathworks.com)

I finished generating the bitstream file, programmed it to the board and then restarted.

When I used h = aximanager('Xilinx',' interface','pcie'); command, the following error occurs:

Error using pciexilinx_mex

Error: There is no compatibility FPGA-in-the-Loop device in the system. You may have not installed the driver required for this operation.

Error in hdlverifier.AXIManagerPCIe/openPCIeConnection

Error in hdlverifier.AXIManagerPCIe

Error in aximanager

Later I thought that I did not install the XDMA driver. After I installed it, the problem was still the same. I would like to ask how to solve this?

I implemented it with vivado 2022.2, matlab R2023b, KCU116 fpga board on windows.

Answer 1

[aditi bagora]

Hello Chia-Cheng,

I understand that you are facing an error while running the example due to a compatibility problem. Often, installing the driver and performing a restart resolves such issues.

However, since you are still facing the same error, there is a possibility that the configuration you have might not be compatible.

Please refer to the provided documentation, which thoroughly outlines the necessary hardware and software specifications.

• https://www.mathworks.com/help/releases/R2023b/hdlverifier/gs/supported-eda-tools.html#:~:text=the%20SGMII%20interface.-,Supported%20FPGA%20Devices%20for%20FPGA%20Verification,-HDL%20Verifier%20supports

I hope the information helps in resolving the issue.

[Chia-Cheng]

Thank you for your information. I saw in it that HDL Verifier does not seem to support the FIL of KCU116. I am thinking that this may be the reason for the error. In this case, I wonder if it will not be possible to implement it with this board.