Rate Transition with a RAM Block

Dear Community,

I am currently struggling to build an HDL System, that uses a Dual Rate Dual Port RAM Block. I have an Input logic that derives its sample time from an ADC Model, that is connected to the input of my digital logic. Now I want my output logic to run at a quarter of that, to allow 1 to 4 rate reduction. I wanted to use a FIFO that specifies an input to output rate transition, to pass the data availability and force the rate transition through that.

I have attached a picture. The magenta highlighted input is the only one that comes with a sample rate, which is inherited from the outside. All other ports in purple are connected to inherited sample times. The red region should derive its sample tiem from the magenta input, which works just fine. The blue region should have four times the sample rate. The only explicit rate transition is in hte fifo in the bottom center.

For simulative purposes I need the sample time to be derived from the outside, so I can simulate the influence of different ADC sample rates. Explicitly setting the time anywhere is of the table. How can I enforce the desired behavior?

Answer 1

[Kiran Kintali]

Can you please share your model? Thanks.