Hi Maria,
To generate a chirp signal using the DDS Compiler 6.0 in Simulink, you'll need to configure the DDS Compiler block to produce a frequency-modulated output. The DDS Compiler is part of the Xilinx DSP System Generator, so make sure you have the necessary toolboxes and licenses installed.
Refer to the following documentation for more information: https://www.mathworks.com/products/dds.html
You can set-up a DDS Compiler to generate a chirp signal by adding a DDS Compiler 6.0 Block in your model. It is found in the Library Browser > Xilinx Blockset > DSP > Signal Generators. Setup the required parameters like Phase Increment, Output Width, and Output Frequency.
To generate a chirp, you need to modulate the frequency over time. This can be done by varying the phase increment dynamically. Use a Counter or Ramp block to generate a time-varying signal that will modulate the phase increment. Then, connect this modulating signal to the Phase Increment input of the DDS Compiler block. The output can then be observed using a Scope block.
Make sure to set the solver to Fixed-step and choose an appropriate step size for your simulation.
For more information refer to the following documentation:
Hope this helps!
