ERROR[-1]: Failed to create buffer for: mwipcore0:s2mm0, Error using matlabshar​ed.libiio.​base/cstat​usid

I’m trying to implement the ADC Data Capture to DDR Memory on the Xilinx Zynq UltraScale+RFSoC ZCU216 Evaluation Kit. I am able to complete the setup part and generate the bit stream and program the device but when I run the HostIOs_rfsocADCDDR4Capture_interface file to see the output, I’m getting these errors

ERROR[-1]: Failed to create buffer for: mwipcore0:s2mm0

Error using matlabshared.libiio.base/cstatusid

Failed to configure device and buffers.

Error in matlabshared.libiio.base/setupImpl

Error in matlabshared.libiio.axistream.read/setupImpl

Error in fpgaio.driver.AXIStreamIIORead/setup

Error in fpgaio.interface.AXI4Stream/setup

Error in fpgaio.interface.AXI4Stream

Error in fpgaio.FPGA/addAXI4StreamInterface

Error in gs_gm_rfsocADCDDR4Capture_setup (line 164)

addAXI4StreamInterface(hFPGA, ...

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Error in gs_gm_rfsocADCDDR4Capture_interface (line 27)

gs_gm_rfsocADCDDR4Capture_setup(hFPGA);

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

And once this happens the entire system crashes and the board stops responding. And if I reboot and check iio_info , again the board crashes so the problem seems to be something with libIIO but I am using the image from Matlab’s SoC Blockset hardware setup process so I am surprised that the base image seems to not be functioning.

Any advice on how to deal with this issue? Because the system crashes simply on trying to check IIO information when running iio_info, the information I can provide on IIO’s status be limited.

[Max]

I am having an identical issue to you. Did you manage to fix it?

Answer 1

[Bhanu Medasani]

There are several reasons why this issue might occur, primarily due to the absence of the necessary clocks for the RFDC block to function correctly. Please consider the following steps to troubleshoot the problem:

1.CLK104 Add-In Card Connection:

Ensure that the CLK104 Add-on card is properly connected to the base board. Can you verify if the CLK104 Add-on card is installed on your ZCU216 Evaluation Board?

2.RFDC IP Configuration:

The RFDC IP might not be configured correctly during boot-up. The `rfinit` process is responsible for configuring the RFDC IP at startup. You can check the proper RFDC IP configuration by checking the serial terminal of the target during boot up .

3.MATLAB RFDC Configuration Script:

The RFDC configuraiton can also be done from MATLAB, try running the RFDC configuration script from MATLAB to identify any errors during the RFDC configuration process.

During the initialization of the RFDC, an `rf_init.log` file is generated in the `/mnt` folder on the target device. If the issue persists, please share the `rf_init.log` file for further analysis.

[Sergei]

Hello @Bhanu Medasani,

What relation does the RFDC configuration have to this question? @Srishti gets an error during the attempt to run the host-interface script, this happens after the RFDC and the FPGA are already programed.

[Bhanu Medasani]

For normal SoC designs the source clock for the DUT is derived from the PL Clocks, however in the case of RFSoC designs where we enable the RFSOC IP the clocks to the DUT is derived from the RFSOC IP. Down the line on the PS side or the HOST I/O we use the libiio framework to read and write sample or to interacting the DUT. So in this scenario if the RFDC is either not configured properly which either could be due to a faulty RF configuration or due to CLOCK 104 not being installed then the DUT is not clocked properly. As the RFDC configuration happens on the hardware, there is no check if it was successfully completed or if it has failed. In the failed scenario the system freezes as there is no DUT clock , DMA does not transfer the data to memory, and the SW is waiting for buffers to be available. This is triggered only when we either run the SW model on the PS or through the FPGA I/O.