Difference in resource utilization using HDL Coder

1. Using MATLAB:I have wriiten code in MATLAB HDL coder and it generated synthesized results successfully (connected Vivado internally)

1. Xilinx Vivado: For same logic i have written a verilog code and synthesized directly in Vivado and got synthesized results.

Result: HDL coder (MATLAB code) requires more resources compared to direct synthesis using Vivado(verilog code).

Querry: Why this difference appeared even in both the places I have used same logic?

Answer 1

[Sahas]

Hi @Achala G,

When you write code in Verilog on your own the implementation can be different as the code you might have written is more optimized and starightforward to your use. On the other hand, the code generated by MATLAB is fairly generic and less optimized. This is the reason that you can see difference in resourse estimation.

For more information to estimate FPGA resource utilization using MATALB, refer to the following MathWorks documentation on the function "estimateResources": https://www.mathworks.com/help/deep-learning-hdl/ref/dlhdl.processorconfig.estimateresources.html

I hope this is beneficial!