Does signal logging strategy affect model execution time?

I have a large model that runs at a small time step which outputs a bus of many signals all in the same time base. I'm looking to optimize execution time & can choose to use a root level outport or signal logging to extract the data. For signal logging I can also choose between decimation and defining a sample time in the signal properties editor to reduce number of data points. For root level outport it seems I can only choose decimation.

Will one method yield faster execution times than the other?

Answer 1

[Spruha]

Hello Allen,

I see you want to speed up your simulation by changing how you export data. Both signal logging and outports can be used to extract data from your model.

With signal logging:

• Decimation allows you to log every Nth data point. This reduces the amount of data you save, which helps with memory usage, but It does not make the simulation run any faster—all signals are still calculated at every time step.
• Sample time works differently. If you set a slower sample time for a logged signal (and that signal isn’t needed elsewhere at a higher rate), Simulink can compute and log it less frequently. This can help reduce both the exported data and the simulation time.

For outports, the only option to reduce exported data is decimation (logging every Nth point). Like with signal logging, this only reduces the amount of data you store, not the simulation speed.

So, adjusting the sample time for signal logging can be used to optimize the simulation time.

You may refer to following documentation to learn more about decimation and sample time for signal logging:

• https://www.mathworks.com/help/simulink/gui/signallogging.html
• https://www.mathworks.com/help/simulink/gui/decimation.html
• https://www.mathworks.com/help/simulink/ug/how-to-specify-the-sample-time.html

Hope this helps!

[Allen]

Thanks!

In this case I have a fixed solver step size, so decimation and sample time would be equivalent?

(of course assuming the decimation parameter is set to yield the same sample time)

[Spruha]

In fixed-step solver signal is computed at the base sample time (i.e., the solver step size), then decimation and sample time for logging are equivalent—as long as the decimation factor and the sample time result in the same logging interval.