Deploying CNN model on FPGA DE0 Nano Board

Hello,

I am planning to deploy a CNN on my FPGA DE0 Nano Board (Cyclone IV), which is a custom board not directly supported by MATLAB. I have made myself comfortable with HDL Coder in Simulink by working on FIL (FPGA-in-the-loop) workflow for video processing application and hence I am looking for a similar workflow using Simulink, HDL coder, etc.

Could you outline the exact steps to follow on how do I go about developing a simple model using Simulink (maybe start with SqueezeNet to begin with on Deep Network Designer), making it hardware compatible and the process to deploy it on my FPGA? The resources available online talk about IP core generation, etc, which are a bit confusing and overwhelming.

Thanks :)

Answer 1

[Aabha]

Hi @Parthsarthi,

Here are a few steps you can follow in order to develop a Simulink model of a CNN, and make it compatible with target hardware:

1. Use the ‘Deep Learning Toolbox’ in MATLAB to build networks from scratch using MATLAB code or interactively using the ‘Deep Network Designer’ app. Please refer to the below documentation link for more information regarding the same: https://www.mathworks.com/help/releases/r2024b/deeplearning/build-deep-neural-networks.html. Once you have the deep learning model, you can use the ‘Deep Learning Toolbox’ to export the network to a Simulink model. Alternatively, to generate a Simulink model that uses the ‘Deep Learning Layers’ block library to represent a network, use the‘exportNetworkToSimulink’function. This function creates a Simulink model for a trained ‘dlntwork’ object. Please refer to the following documentation link for more information about the function: https://www.mathworks.com/help/releases/r2024b/deeplearning/ref/dlnetwork.exportnetworktosimulink.html You can also refer to the following blog post on integrating machine learning models with Simulink models: https://blogs.mathworks.com/deep-learning/2024/06/24/export-models-from-machine-learning-apps-to-simulink/
2. Use fixed-point conversion to make the model compatible with FPGA hardware. Please refer to the following documentation link for more information about converting a model to fixed-point: https://www.mathworks.com/help/releases/r2024b/fixedpoint/ref/fixedpointtool.html Additionally, make sure that all the blocks used in the Simulink model are compatible with HDL Coder. You can also try designing an independent model using blocks from the ‘Deep Learning HDL’ Toolbox.
3. Use the ‘HDL Workflow Advisor’ for checking the model for HDL code generation compatibility and automatically fixing incompatible settings. The ‘HDL Workflow Advisor’ will guide you through the stages of generating HDL code for a Simulink subsystem, and the FPGA design process. Please refer to the below documentation link for detailed information about the same: https://www.mathworks.com/help/releases/r2024b/hdlcoder/ug/using-the-hdl-workflow-advisor-window.html

I hope this helps.