Error about simulink model convert to state-space model for HIL

When I create a DC-AC inverter model and use 'sschdladvisor' to convert it to a state-space model, setting the input to boolean with fixdt(1,14,11), the output signal matches the original Simulink model before conversion.

However, when I create a DC-DC CLLC converter and convert it to a state-space model, the output signal shows an overflow error. Even after adjusting the fixed-point values of the MOSFET gain, the signal still overflows.

Use 'sschdladvisor' generate 32 or 48 word length fixed point are both occur overflow, when using CLLC model.

I want to ensure the result is correct because I plan to use the state-space model to generate IP code, which will then be deployed with Vivado for HIL testing.

Answer 1

[Harsh]

Hi @Xiang,

From what I can gather, you are encountering overflow errors while using Simulink and the "sschdladvisor" tool to convert your DC-DC CLLC converter model to a state-space model with fixed-point data types, particularly “Wrap on overflow detected” warnings and assertion failures, even when increasing the fixed-point word length to 32 or 48 bits.

The following error means that the value calculated at this point is too large (or too small) to be represented, and instead of being “clipped” (saturated), it wraps around, which can lead to incorrect simulation and hardware results.

>>> [Wrap on overflow detected. This originated from 'gmStateSpaceHDL_CLLCT5_fixpt/.../Gain1']

Here, I would recommend you to use the the Fixed-Point Tool to analyze the minimum and maximum values of signals, especially at the points where overflow is reported (e.g., after Gain blocks).

Simulate your model in double precision and log the min/max values for all relevant signals.

If your signal range is larger than what your current data type can represent (for example, ±64 for fixdt(1,32,25)), you need to allocate more bits to the integer part.

Try reducing the fraction length and increasing the integer length. For example:

• If your signal can go up to ±100, use fixdt(1,32,20) (which covers ±2048) or even fixdt(1,48,30) for larger ranges.
• If necessary, increase the overall word length, but always ensure enough integer bits for your signal range.

Additionally, in your model settings, change the “saturate on overflow” option to prevent wrap-around errors by clamping values at the maximum/minimum representable values. (refer to the following screenshot, in first graph I used fixdt(1,16,15) and in the second one I used fixdt(1,48,30)).

I would recommend you to check out the following documentation and example, it talks about handing overflows in Simulink models,

https://www.mathworks.com/help/fixedpoint/ug/handle-overflows-in-simulink-models.html

Also, feel free to use the following MathWorks documentations to know more about the Fixed-Point Tool:

• https://www.mathworks.com/help/fixedpoint/gs/converting-to-fixed-point.html
• https://www.mathworks.com/help/fixedpoint/overflow-and-precision-loss-detection.html
• https://www.mathworks.com/help/fixedpoint/testing-and-debugging.html

I hope this helps, thanks!