Help to understand RF Data Converter clocking

Dear all,

I am starting to use SoC Blockset add-on and now figuring out how RF Data Converter block works.

For example I set the following parameters in RF Data Converter:

(Sample rate 1024 MSPS, Interpolation/Decimation 1, Samples per clock cycle 4 --> Stream Clock Frequency 256MHz)

The FPGA sampling time is also set to 7.1825e-9 to correspond to Stream Clock Frequency of 256MHz.

Then, in the timing manager we can see, that the RF Data Converter transmits (updates the output dacTxChy) with Stream Clock Frequency of 256MHz.

Now we can set Interpolation/Decimation to 2 (This changes Stream Clock Frequency to 128MHz. The FPGA sampling time is unchanged.

We can now see, that RF Data Converter updates the output dacTxChy with Stream Clock Frequency of 128MHz. This "eats" some of the FPGA samples, which is bad, so I am not sure this is how I should use this block.

The question is what Interpolation setting is done for and how to apply it? Is this ok that when I set the Interpolation parameter to the value different from 1 it seems like the actual sampling frequency just decreases without any benefits? Why not then just decrease Sample rate of RF Data Converter? Thank you!

Answer 1

[Sanjay Boorle]

Hi @Sergei,

The FPGA sample time must always match the stream clock frequency shown on RF Data Converter block mask. From 23b, when you select "Behavioral" simulation mode, the block errors out if they do not match when you do model update or run simulation. The effect of interpolation/decimation mode is observed in simulation, only when you select "Behavioral" simulation mode. The interpolation filters interpolate the DAC input data by a factor selected in the block mask.

The RFDC block operates in frame mode, so the output sample time always matches the input, but the size of the data changes in "Behavioral" simulation mode. When samples per clock cycle is 4 and interpolation mode is 1, then size of the DAC output is 4x1 (a vector/frame with 4 elements). When samples per clock cycle is 4 and interpolation mode is 2, then size of the DAC output is 8x1 (a vector/frame with 8 (4*2) elements).

Hope this clarifies.

Thanks.

[Sergei]

Thank you! This is a perfect explanation.

[Sergei]

So am I correct that the "Behavioral" simulation mode of RFDC is closer to what we will observe after the deployment?

[Sanjay Boorle]

Yes, you are correct.

[Sergei]

Good to know!