long time duration simulink simualtion stopped with error

An error occurred during simulation and the simulation was stopped

Caused by:

• Output sample times of /Integer N PLL with Single Modulus Prescaler/Single Modulus Prescaler/Logic Decision1 occur out of sequence. Specify the 'Minimum delay value' parameter as a value greater than 1e-15 times the simulation stop time.

Component:Simulink | Category:Block error

[Jeff Yan]

any sugg. welcome

[Jeff Yan]

this error happens to the simulink model from the library, which i can't set the minum delay of it.

please help if you know the solution. tired to set time step to 1e-12, not help.

thanks

jeff

Answer 1

[Tridib]

Dear @Jeff Yan,

The error you are encountering is caused by certain blocks in your model that contain internal “Logic Decision” blocks. These "Logic Decision" blocks internally enforce a very small default “Minimum delay value” (typically hardcoded to 1e‑15 seconds). For models using very fine‑grained timing or very small sample steps, this default delay may become too small relative to the model’s simulation stop time, leading to the “sample times occur out of sequence” error.

To resolve the issue, follow the steps below:

• Break the library link for the affected blocks within the Integer N PLL with Single Modulus Prescaler subsystem.
• Select each of the affected blocks individually.
• Then run the following command in the MATLAB Command Window:

 set_param(gcb,'LinkStatus','none')

• Navigate inside the blocks and locate the internal "Logic Decision" blocks.
• These blocks have a mask parameter named “Minimum delay value”.
• Increase the “Minimum delay value” from its default (1e‑15) to a larger number. For example: 1e-13 or, more generally: any value > (1e‑15 × simulation stop time)
• Update and save the model.

After applying these changes, the sample‑time ordering issue should be resolved, and the simulation should run without the timing conflict.

Hope this helps!

[Jeff Yan]

Hi @Tridib. thanks so much for your feedbacks.

i did change the minimum delays (inside the model of integer N PLL) from 1e-15 to 1e-10!

However, the error still exisits, and the sim. time stops at 16sec.

"An error occurred during simulation and the simulation was terminated

Caused by:

Scheduled hit time 16.000004899097814 is less than the current time 16.000004899097814 for rate with index 7 and identifier /Single Modulus Prescaler/Logic Decision1$0."

Please help again.

thanks

Jeff

[Jeff Yan]

problem resolved. i made a mistake forgotting to change the minimum delay value of the last 'logic decision' block.

thanks @Tridib

regards,

jeff