Docblock within a Black box subsystem for VHDL module simulation

Hi, I want to simulate VHDL modules in simulink by using DocBlock. The idea is to compare performance between different designs.

I noticed this topic (Integrate Custom HDL Code by Using DocBlock - MATLAB & Simulink) where I believe it mentions some procedure. Unfortunately I am not able to perform a basic simulation with a VHDL code. I follow the procedures, I add the docblock and then I do not know if I need to add something else in the module.

Is there any particular example with a basic VHDL module process ( let's say a comparator of two inputs, one output) ? From there I would be able to scale.

Answer 1

[Umar]

Hi @Matias,

Thanks for your question — this is a very common point of confusion and the documentation doesn't make it obvious, so let me break it down clearly.

WHY YOUR SIMULATION ISN'T WORKING

The root issue is that DocBlock is purely a code generation tool. When you press Run in Simulink, the VHDL inside the DocBlock is completely ignored — Simulink has no ability to execute VHDL natively. The DocBlock text only matters when you run makehdl to produce HDL output files. So no matter how correctly you've followed the procedure, the VHDL logic will never compute anything during simulation.

TWO DIFFERENT WORKFLOWS — AND WHICH ONE YOU NEED

There are two goals that are easy to mix up, and they require completely different setups:

1. Functional simulation (does the logic behave correctly?) — You need regular Simulink blocks inside the black box subsystem. For your comparator, that means wiring a Relational Operator block (set to ==) between inputs A, B and output EQ. That's what Simulink actually runs. The VHDL sits alongside it for generation purposes only.

2. Simulating actual VHDL code — For this you need HDL Verifier (a separate licensed product) plus an external HDL simulator like ModelSim, QuestaSim, or Vivado Simulator. Simulink sends signals to the external tool, the VHDL runs there, and results come back into Simulink. This is called cosimulation and it's a more involved setup.

THE LICENSE SITUATION

This is rarely explained upfront. To follow the DocBlock workflow as documented, you need HDL Coder licensed. Without it, the HDL Block Properties dialog won't show the Architecture or TargetLanguage options at all — so you can't set BlackBox or HDLText. If those dropdowns aren't appearing, a missing HDL Coder license is likely why. For cosimulation, you additionally need HDL Verifier on top of that.

THE CLOCK PORT GOTCHA

If your VHDL entity has a clk port, there's no direct equivalent in a Simulink black box interface. In Simulink, clock is implicit and derived from block sample time — not an explicit signal. HDL Coder adds clock and reset ports automatically during code generation. This means your VHDL entity interface and your Simulink subsystem port list need to be reconciled carefully, or your port mapping will silently misalign.

ABOUT YOUR PERFORMANCE COMPARISON GOAL

Simulink simulation won't give you hardware performance numbers. It tells you about functional correctness only. Metrics like maximum clock frequency, LUT usage, logic depth, and timing slack come from synthesis tools like Vivado or Quartus — after you run makehdl and import the generated files. The actual workflow for comparing designs is: generate HDL via makehdl for each variant, synthesize each in your FPGA tool, and compare the post-synthesis reports.

RECOMMENDED PATH FOR YOUR COMPARATOR

Here's the simplest working setup to get you started:

• Create a Subsystem and set Architecture to BlackBox in HDL Block Properties • Add ports A, B (inputs) and EQ (output) • Inside the subsystem, add a Relational Operator set to == for simulation behavior • Add a DocBlock, set Architecture to HDLText and TargetLanguage to VHDL, and paste your entity code • Run simulation normally — it will use the Relational Operator • Run makehdl when you want to produce the actual VHDL file

This gives you a working simulation and proper HDL generation from the same model, which is the intended workflow.

Hope this clears things up. Feel free to follow up if you run into issues with the cosimulation setup or port mapping.