we are getting below error, when i am trying to generate verilog code from HDLIFFT model. Please help to understand/resolve this error.

Expected InputPortVectorSize to be an array with all of the values >= 8. The error occurred for MATLAB System block 'IFFT_HDL2/IFFT HDL Optimized'. See line 1, column 1 in file 'C:\Program Files\MATLAB\R2014b\toolbox\dsp\dsp\+dsp\+private\AbstractHDLFFT.p'.
Component: Simulink | Category: N.A.

Error in port widths or dimensions. Output port 1 of 'IFFT_HDL2/Source' is a [8x1] matrix.
Component: Simulink | Category: N.A.

Answer 1

[Bharath Venkataraman]

For HDL code generation, the HDL IFFT block requires the input to be fed in one sample at a time. Please serialize the data and feed in one sample at a time.