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Can anyone explain the relationship between simulink sampling time and real world clock in FPGA?

1 vue (au cours des 30 derniers jours)
Hello.
Can anyone explain the relationship between simulink sampling time and real world clock in FPGA? I'm working with FPGA Cyclone IV, Matlab 2014b.

Réponses (1)

Ganesh Gaonkar
Ganesh Gaonkar le 12 Juin 2015
Hi,
This example from MathWork's HDL Verifier Toolbox can give you a good idea on the relation between Simulink Sample Time and FPGA clock ticks.

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