Generate model from existing vhdl entity

I have a question regarding HDL Coder which we are evaluating right now. How can I set up an model from an existing VHDL entity. The interface should be created automatically from the architecture. Tried to find that in the docs, but could not find a solution to that.

Answer 1

[Tim McBrayer]

The ability to do this automatically is not currently part of Simulink HDL Coder. It can be done manually, though, by building a subsystem with the desired IO interface as part of your larger HDL model. You should choose "BlackBox" for the HDL Block Architecture property. Simulink HDL Coder will generate a component instantiation using the names, ports, data widths, and so forth, from the BlackBox subsystem, integrated into your larger code generation model. It will not generate any code for the contents of that subsystem.

Answer 2

[P. Fetzer]

But what if my workflow includes Simulation with external tools like ModelSim. Does that mean I cannot simulate my model directly because I have an black box that is not connected to my entity in any way?