Simulink- Zynq-7000 several AXI interfaces in the Simulink peripheral
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Hello, I am working with the ZedBoard, HDL coder and embedded coder. In order to be able to interact with the IP created by Simulink in parallel from the two ARM cores, I would like to add an additional AXI interface both to the Simulink IP and to the SW interface. Does anyone know how to do that? I created a bridge IP in the reference design in Vivado connected to the Simulink IP but I don't know how I can add this second AXI interface to be accessible from the SW model.
Noam Levine on 16 Oct 2015
Edited: Noam Levine on 16 Oct 2015
In order for the new reference design (with the additional AXI interface) to be recognized in the hardware/software workflow, which will then let you generate an interface model with the appropriate interfaces, you need to register the reference design per http://www.mathworks.com/examples/matlab-hdl-coder/12209-define-and-register-custom-board-and-reference-design-for-soc-workflow