What are the advantages and limitations of different workflows when targeting the PicoZedSDR (specifically the FPGA and AD9361) for prototyping and designing radios?
- I see there is a Zynq Radio HSP (aka "Radio-in-the-loop") that may or may not be able to even use the radio.
- There's the FPGA-in-the-loop workflow that doesn't use the radio.
- Then we're left with the IP Core Workflow (HDL Coder -> Vivado IP Integrator?)
- and the HW/SW Codesign Workflow (Mathworks Software -> Vivado and Xilinx SDK?)
According to the " FPGA Targeting Overview " documentation, "FPGA targeting support is available for both the receive path and the transmit path, one at a time." At what level is this true, and is it true for all Mathworks-supported Zynq-based hardware using AD936X radios?
It also says, under "Limitations" at the bottom:
Transmitter FPGA targeting does not support multirate I/O. Receiver FPGA targeting does support downsampling.
Transmitter FPGA targeting and receiver FPGA targeting do not support resource sharing.
The use of tunable parameters is not currently supported in the FPGA targeting workflow.
Is this also true for all Mathworks-supported Zynq/AD936X hardware combos?
Thanks for your time. Any clarification would be greatly appreciated!!!