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Support and Limitations using Mathworks Software w/ Avnet PicoZedSDR

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What are the advantages and limitations of different workflows when targeting the PicoZedSDR (specifically the FPGA and AD9361) for prototyping and designing radios?
  • I see there is a Zynq Radio HSP (aka "Radio-in-the-loop") that may or may not be able to even use the radio.
  • There's the FPGA-in-the-loop workflow that doesn't use the radio.
  • Then we're left with the IP Core Workflow (HDL Coder -> Vivado IP Integrator?)
  • and the HW/SW Codesign Workflow (Mathworks Software -> Vivado and Xilinx SDK?)
According to the " FPGA Targeting Overview " documentation, "FPGA targeting support is available for both the receive path and the transmit path, one at a time." At what level is this true, and is it true for all Mathworks-supported Zynq-based hardware using AD936X radios?
It also says, under "Limitations" at the bottom:
Transmitter FPGA targeting does not support multirate I/O. Receiver FPGA targeting does support downsampling.
Transmitter FPGA targeting and receiver FPGA targeting do not support resource sharing.
The use of tunable parameters is not currently supported in the FPGA targeting workflow.
Is this also true for all Mathworks-supported Zynq/AD936X hardware combos?
Thanks for your time. Any clarification would be greatly appreciated!!!
- Rich

Accepted Answer

Neil MacEwen
Neil MacEwen on 13 Nov 2015
Hi Richard,
The Zynq Radio HSP will let you stream data into and out of MATLAB from any supported Zynq + AD936x radio platform. This includes PicoZed SDR and any combination of ZC706/ZedBoard with an FMCOMMS2/3/4 RF card. All hardware platforms have the same feature set and limitations. From MATLAB or Simulink you can configure the RF front end and start transmitting or receiving data; there are advanced I/O modes available such as looping transmit mode or burst mode for capturing high bandwidth signals. The HSP currently allows you to target the FPGA portion of the Zynq chip, either the transmit or receive path, one at a time. Once you have your algorithm on the FPGA, the same I/O streaming features are all still available to test your IP.
The other workflows you mention are general FPGA or HW/SW flows, currently with no specific radio functionality.
Hope this helps,
Neil

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