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How to specify sample rates for Xilinx Zynq-Based Radio?

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Johannes Kopp
Johannes Kopp on 8 Nov 2016
Answered: Neil MacEwen on 15 Feb 2017
I am using Matlab 2016a and the support package Communications System Toolbox Support Package for Xilinx Zynq-Based Radio to create a FM demodulation algorithm, which can be translated into HDL-Code and run on the FPGA of a Xilinx Zedboard. The RF FMC card I use is the Analog Devices AD9364.
The algorithm works in simulation, but when trying to get it onto the FPGA, I've got a problem with the sample rates. Basically, I want the FPGA to work on a high rate (preferably 960kHz, but the exact rate is not important) and then downsample the signal to a lower rate (48kHz) before sending it to the host PC via Ethernet. Now the question is, how do I specify those two sample rates?
In the SDR Receiver Block, which acts as the interface towards the board, I see only one rate that can be changed ("Baseband sample rate (Hz)"). The documentation states that this is the Simulink sample time, not the sample time of the board [1]. However, that rate can not be set below 520.841kHz, which I find to be irritating. Why can I not set the Simulink sample time to any value I like? Besides, I cannot find another field to specify the rate of the FPGA.
If you know anything that could help me, please take the time to write it down. Thank you very much!

Answers (1)

Neil MacEwen
Neil MacEwen on 15 Feb 2017
Hi Johannes,
Apologies for the delay in responding. Unfortunately you are hitting a limitation in the FPGA-only targeting workflow, where the sampling rate must be consistent from the RF card right through to Simulink.
From April 2016, in R2016a, the HW/SW co-design workflow would allow you to work around this limitation. In this workflow, although the rates at the input and output of the user logic must still be the RF clock rate you can explicitly model the valid signal at the output of the user logic, and configure the ARM processor to sample the FPGA for samples at any desired rate. Note that this workflow requires the Embedded Coder support package for Xilinx Zynq.
I hope this helps,

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