I am using Matlab 2016a and the support package Communications System Toolbox Support Package for Xilinx Zynq-Based Radio to create a FM demodulation algorithm, which can be translated into HDL-Code and run on the FPGA of a Xilinx Zedboard. The RF FMC card I use is the Analog Devices AD9364.
The algorithm works in simulation, but when trying to get it onto the FPGA, I've got a problem with the sample rates. Basically, I want the FPGA to work on a high rate (preferably 960kHz, but the exact rate is not important) and then downsample the signal to a lower rate (48kHz) before sending it to the host PC via Ethernet. Now the question is, how do I specify those two sample rates?
In the SDR Receiver Block, which acts as the interface towards the board, I see only one rate that can be changed ("Baseband sample rate (Hz)"). The documentation states that this is the Simulink sample time, not the sample time of the board . However, that rate can not be set below 520.841kHz, which I find to be irritating. Why can I not set the Simulink sample time to any value I like? Besides, I cannot find another field to specify the rate of the FPGA.
If you know anything that could help me, please take the time to write it down. Thank you very much!