IP Core genration in hdl coder for Zedboard FMCOMMS2 Channel Mapping
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pooria varahram
le 9 Fév 2017
Réponse apportée : Neil MacEwen
le 10 Fév 2017
Hello,
There are no settings for channel mapping and DUT synthesize frequency in hdl coder of Zedboard and FMCOMMS2. This exists in simulink hdl coder workflow but not in m file. Could you please tell me how could I set these parameters?
Best Regards, Pooria Varahram.
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Neil MacEwen
le 10 Fév 2017
Hi Pooria,
I'm afraid the the targeting workflow is only supported from Simulink. You could try including your m-code in a MATLAB Function block .
Regards,
Neil
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Neil MacEwen
le 10 Fév 2017
Hi Pooria,
Thanks for your question. I need some more information on what you are trying to do to be able to answer your query accurately.
The channel mapping and DUT synthesis frequency parameters are available in both the FPGA targeting and HW/SW co-design workflows using the HDL Workflow Advisor. The DUT synthesis frequency parameter is only applicable to the targeting workflows. The channel mapping parameter is used for targeting workflows but also in I/O modes where you are trying to stream data into or out of MATLAB/Simulink using System Objects or Simulink blocks.
I am unclear if you are trying a targeting workflow or are trying to stream data into or out of Simulink. Could you please let me know which version of MATLAB you are using and exactly what you are trying to do?
Thanks,
Neil
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