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pooria varahram


Actif depuis 2017

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Question


IP core generation zedboard FMCOMMS2 gives 2 critical warning in Vivado
Hello, When I open the project generated from matlab example HW/SW Co-design QPSK in Vivado it has 2 critical warning in timi...

environ 7 ans il y a | 1 réponse | 0

1

réponse

Question


IP Core genration in hdl coder for Zedboard FMCOMMS2 Channel Mapping
Hello, There are no settings for channel mapping and DUT synthesize frequency in hdl coder of Zedboard and FMCOMMS2. This exi...

environ 7 ans il y a | 2 réponses | 0

2

réponses