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[Zynq ad9361 fmscomms2] Frame Size increase

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hoang viet
hoang viet on 17 Sep 2017
Commented: Neil MacEwen on 2 Oct 2017
I'm working in a project related to design a SDR communication system to streaming video used on QPSK modulation.
Hardware is ad9361 fmscomms2 with zedboard
And i have some question about the interface model example
  • In the data generation part as i understand in the "for iterationsubsystem" we packing 200xdouble same message data (154 data + 26barker code + 20 bernoulli i will call it a packet)x50 times toconstruct 10000xdouble data frame length.
Can I change it to packing only one packet without iterator the same packet data.
Because I planning to support ethernet frame with MTU is 1500. The message data now is 22 bytes (Zynq HW/SW Co-design) and I want to increase it.
  • Another problem is when data is transfer from ARM to PL and PL toARM through DMA we alway get a error in first bytes. When I select srcselect from ARM. And I don't know why.
Many thanks.

Accepted Answer

Neil MacEwen
Neil MacEwen on 19 Sep 2017
Hello, yes you can change the data packet size that is sent to the transmitter. In the example, the software running on the ARM is scheduled on the transmitter interrupt, meaning that all the blocks in the model will execute on the ARM when the transmit interrupt fires, which happens after each data frame is sent. If the data frame size is too small, the interrupt will fire too often and the ARM will not run well. This is why the data is buffered into a larger frame size. Have a good read of the software interface model setup documentation and the system timing information.
In your case, you should consider the information in the documentation and your system timing requirements (frame size and frame rate) and set up your model accordingly. As a general rule, we advise that you keep the schedule rate of your model below 5kHz.
Kind regards,
Neil MacEwen
Neil MacEwen on 2 Oct 2017
You are correct, in the configuration of this model the data size is limited to fit into the packet. If you are trying to build a custom packet type, or size, you may need to change the transmitter in a few places.
The schedule rate is the fastest rate in your model. In this case, it is the frame rate at the input to the transmitter which is set in the rate transition block. The same rate is configured on the receiver part in the sample time specification block, and on the FPGA interface section on the constant source.

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