how to simulate FFT HDL optimized?

I created a simulink project containing "FFT HDL optimized block" and I converted it to HDL code by using Hdl coder.Then, I created testbench for it by using the option of "generate testbench" at Simulink. However, when I simulated the testbench, I encountered a problem at simulation.Simulation results are correct between 480 ns and 560 ns(I started to take data out from 480 ns because of latency of the FFT block).From 560 ns, the simulation started to give error according to expected data out value.How can I solve the problem? FFT Length of the Block=16 Clock Time=10 ns

Answer 1

[Alireza]

Hi, I could reproduce the failure in R2015a. But it is not reproducible is R2016a. It seems that the bug is fixed in R2016a release. Can you use/upgrade to R2016a and try your model Thanks Ali

Answer 2

[Alireza]

Hi, Would you please attach your model? Thanks Ali

[Berat Atmaca]

[Berat Atmaca]

Thanks

[Berat Atmaca]

I cannot add the simulation image because of the daily limitation of the mathworks. As I said at yesterday, in simulation I start to take output at 480 ns. And the output is correct until 560 ns. After 560 ns, there is difference between the simulation results and expected results.

Answer 3

[Alireza]

Hi, I believe you are using R2014a. If you provide the input data type, I can check if it is fixed in later versions. I recommend to use R2016a version or later. We made a big performance improvement to the block at that release and added frame support.

[Berat Atmaca]

To see output characteristics of the FFT HDL optimized block, I create simple project contains FFT block and random signal generator feeds the FFT and Input data type is int16.

[Berat Atmaca]

I will shortly mention about the process: Firstly I created a project contains FFT and signal generator in simulink. Then, I converted it into HDL CODE by using hdl coder in simulink.I ran the code in xilinx vivado. After that, I created testbench by using option of "generate testbench" of simulink. Finally, I added the testbench file to vivado and simulate it. The simulation results was like as that I mentioned above.(Version:R2015a)

PS:In addition to that, I created very very simple project making addition and subtraction without FFT to test whether it works.And I saw that it works correctly.