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How do I assign external ports in the Workflow Advisor for the ADRV9361-Z7035 evaluation board mounted on the ADRV1-CRR-BOB

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Christian Amey
Christian Amey on 10 Jun 2019
Answered: JT Ferrara on 1 Jul 2021
I've been working with the ADRV9361-Z7035 / ARDV1-CRR-BOB combo for a little while in Simulink and now am trying to build the bitstream and assign some data signals to some external ports. I thought all I had to do was assign the Port Name that was defined in my project to the correct FPGA pin ('V18' for IO_25_13_JX2). The system_wrapper.bit file is generated and downloaded to the ADRV9361-Z7035 board, then I open the software interface model that is created during step 4 of the HDL Workflow Advisor and attempt to run the project in External mode. The project builds successfully and indicates it is running on the hardware, however, I don't observe any data on the corresponding pin. Have I forgotten to enable/addres a key part of the design process?
EDIT: We also checked all breakout connections on headers P2 and P3 of the BOB. The data type assigned to the external target interface was an unsigned fixed 1-bit output (ufix1). We specified a cell array of {'V18'}.

Answers (1)

JT Ferrara
JT Ferrara on 1 Jul 2021
Hi Christian,
Based on your description, it sounds like you are correctly specifying the external ports. Can you please check that the corresponding constraints file is generated? You can locate this file in the "hdl_prj/vivado_ip_prj" folder with the XDC extension.
If you are still facing this issue, please reach out to MathWorks Technical Support at support@mathworks.com.

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