Why do I get the error message "Run 'impl_1' has not been launched. Unable to open" when using HDL Coder, HDL Verifier or SoC Blockset?

When I try to run "HDL Workflow Advisor", "SoC Builder", or the "Verify Setup" test during the "HDL Verifier Support Package for Xilinx FPGA boards" hardware setup, the programming file generation fails for my Xilinx board. The error below is thrown in MATLAB or in the Vivado build log (vivado_build_prj.log). Why is this?

ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open  

 

Answer 1

[MathWorks Support Team]

To find out the root cause for this error, open the Vivado Project File (.XPR) in Vivado IDE by double-clicking on it. The .XPR file can be found in locations similar to:

\hdl_prj\vivado_ip_prj\vivado_prj.xpr
\soc_prj\vivado_prj.xpr

In Vivado IDE, go to the "Messages" tab to see the exact error message that prevented Vivado from running the synthesis:

Licensing Error

A common error message that you may see is the following:

[Common 17-345] A valid license was not found for feature 'Synthesis' and/or
device 'xc7z045'.
Please run the Vivado License Manager for assistance in determining which
features and devices are licensed for your system.

This means that your Vivado installation does not have the appropriate license to run the synthesis for your targeted device.

Please note that the free Vivado WebPACK edition (since 2021 called "Vivado ML Standard") only supports low-cost devices, such as the 'xc7z020' Zynq device used on the Zedboard or Xilinx ZC702 evaluation board. To target high-cost boards like Xilinx ZC706, Xilinx ZCU102 MPSoC, or Xilinx ZCU216 RFSoC, you will need an appropriate Vivado enterprise license.

A list of all FPGA devices supported by Vivado WebPACK can be found in the "Architecture Support" section of the Vivado Design Suite Release Notes. For the most recent version, please refer to this XLINX documentation on compatibility.

https://www.xilinx.com/products/design-tools/vivado/vivado-buy.html#architecture

To resolve this, contact your company's license administrator to get an appropriate Xilinx Vivado license for your FPGA device.

Cache Error

Another possible error message shown below, that may occur during HDL Verifier validation:

ERROR: [Common 17-1293] The path '<path_to_cache>/<cache_name>.cache/wt' already exists, is a directory, but is not writable.

To resolve this, try the debugging steps below:

1) Delete the directory "wt" located at "<path_to_cache>/<cache_name>.cache/wt", then rerun the validation.

2) Try deleting the cache file itself, then rerun the validation.

3) Ensure that Vivado and MATLAB have permission to write in this directory, and that it is not read-only.

4) Ensure that the "wt" directory is not located within a networked or remote drive/directory, which could also cause issues with write permissions.