Communication from processor (PS) to the FPGA (PL) via AXI4-lite

We are using a Zynq SoC FPGA from Xilinx and want to establish a communication from the processor (PS) to the FPGA (PL) via AXI4-Lite. On our processor a linux-based operating system is running and we are using UIOs to access the AXI4-Lite registers of different IP cores. Therefore, we add our IP core in the device tree as followed:

ip_core@43c00000 {

compatible = "custom_ip,generic-uio,ui_pdrv";

reg = <0x43c00000 0x1000>;

xlnx,s00-axi-addr-width = <0x4>;

xlnx,s00-axi-data-width = <0x20>;

};

Now, our question is whether this is the right approach or is there a better option for the communication of the PS and the PL? Is editing the device tree allowed? Or is a device tree overlay a better approach?

Thanks in advance.

Best regards,

Quoc Viet Bui

Answer 1

[Steve Kuznicki]

You can definitely edit the devicetree file. It's up to you if you want to edit the full file or instead use device tree overlays. The Linux image we build should support both.

As Charan points out, there is a "better" way for accessing AXI4-Lite registers from the PS. This would require you to boot the Linux image MathWorks provides in the HDL Coder Xilinx Zynq Hardware Support Package or have the device drivers built and available on your OS (see https://github.com/mathworks/buildroot). This also requires the HDL Coder product and Embedded Coder (for generating C code).

Your devicetree would include the node (adjust phandle accordingly):

mwipcoreMyIPCore@43C00000 {
compatible = "mathworks,mwipcore-v3.00";
reg = <0x43C00000 0x10000>;
#address-cells = <0x01>;
#size-cells = <0x00>;
linux,phandle = <0x94>;
phandle = <0x94>;

mmrd-channel@0 {
    reg = <0x00>;
    compatible = "mathworks,mm-read-channel-v1.00";
    mathworks,dev-name = "mmrd0";
    };

mmwr-channel@1 {
    reg = <0x01>;
    compatible = "mathworks,mm-write-channel-v1.00";
    mathworks,dev-name = "mmwr0";
    };
};

To generate "C" code for your application, use the AXI4-Lite Read/Write Blocks found in the "Embedded Coder Support Package for Xilinx Zynq Platform" Simulink library. In those blocks you can specify the device name (/dev/mwipcoreMyIPCore) and the register offset. You can read/write (uint32) scalar values or vectors but reading and writing vectors requires contiguous register offsets followed by a "sync" register.

Since these drivers utilize IIO (libIIO), it's possible to run a Simulink model in "Normal" mode while communicating with your DUT in the FPGA. That's pretty awesome.

Answer 2

[Charan Jadigam]

Hi,

To communicate between PS and PL using AXI4-lite, Simulink provides support to generate custom IP cores using HDL coder and generate bitstream. You can develop application algorithm using Simulink models and generate c code intended to work on LINUX using Embedded Coder support package for ZYNQ platform.

You can know more about Hardware software co-design workflow here.

Communication between PS and PL using Axi4-lite can be done using AXI-4 interface read/write block in Embedded coder library. The detailed description about process can be found here.